Low-power level shifter for multi-supply voltage designs
In this brief, a new low-power level shifter (LS) is presented for robust logic voltage shifting
from near/sub-threshold to above-threshold domain. The new circuit combines the multi …
from near/sub-threshold to above-threshold domain. The new circuit combines the multi …
Fast and wide range voltage conversion in multisupply voltage designs
Multisupply voltage design technique is widely used in modern system-on-chips to tradeoff
energy and speed. Level shifters (LSs) allow different voltage domains to be interfaced. In …
energy and speed. Level shifters (LSs) allow different voltage domains to be interfaced. In …
A new circuit-level technique for leakage and short-circuit power reduction of static logic gates in 22-nm CMOS technology
M Moradinezhad Maryan, M Amini-Valashani… - Circuits, Systems, and …, 2021 - Springer
The leakage power, aka static power, increases in deep-submicron technologies due to
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories
K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Static or leakage power is the dominating component of total power dissipation in deep
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
Robust logic circuits design using SOI shorted-gate FinFETs
The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
technology has reached to its extremity. Double Gate (DG) device was introduced to derive …
technology has reached to its extremity. Double Gate (DG) device was introduced to derive …
Design of low leakage variability aware ONOFIC CMOS standard cell library
VK Sharma, M Pattanaik - Journal of Circuits, Systems and …, 2016 - World Scientific
In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS
digital standard cell library is developed. The developed standard cell library contains basic …
digital standard cell library is developed. The developed standard cell library contains basic …
Dynamic threshold sleep transistor technique for high speed and low leakage in CMOS circuits
R Lorenzo, S Chaudhury - Circuits, Systems, and Signal Processing, 2017 - Springer
Leakage power dissipation is a serious concern in deep nanometer devices. Low power
design methodology is often adopted in VLSI circuits and systems to minimize power; …
design methodology is often adopted in VLSI circuits and systems to minimize power; …
Adaptive technique for overcoming performance degradation due to aging on 6T SRAM cells
The threshold voltage drifts induced by positive bias temperature instability (PBTI) and
negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These …
negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These …
Reliable and ultra-low power approach for designing of logic circuits
The principal design concern in today's very large-scale integration (VLSI) industry is power
dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation …
dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation …