US7282415B2 - Method for making a semiconductor device with strain enhancement - Google
Patents US7282415B2 - Method for making a semiconductor device with strain enhancement …

The embodiments of mechanisms for forming source/drain (S/D) regions of field effect
transistors (FETs) described enable forming an epitaxially grown silicon-containing layer …

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar
semiconductor device includes a semiconductor body having a top surface opposite a …

2). Discussion of Related Art Integrated circuits are often manufactured in and on Silicon and
other Semiconductor wafers. Such integrated circuits include literally millions of metal oxide …

A contact architecture for nanoscale channel devices having contact structures coupling to
and extending between source or drain regions of a device having a plurality of parallel …

US7479421B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US7479421B2 - Process for integrating …

The present invention relates generally to the field of Semiconductor processing and, more
Specifically, to a fab rication process for a transistor Structure with thick recessed …

According to an embodiment of the present invention, a hard mask material is formed on a
silicon film having a global crystal orientation wherein the semiconductor film has a first …

US8193567B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US8193567B2 - Process for integrating …

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to metal-
oxide-Semiconductor field effect transistors (MOSFETs) and more particularly to transistor …