High-performance interconnects: An integration overview

RH Havemann, JA Hutchby - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI)
have spawned an ever-increasing level of functional integration on-chip, driving a need for …

Organic electronics: introduction

JM Shaw, PF Seidler - IBM Journal of Research and …, 2001 - ieeexplore.ieee.org
For the past forty years inorganic silicon and gallium arsenide semiconductors, silicon
dioxide insulators, and metals such as aluminum and copper have been the backbone of the …

Porous dielectrics in microelectronic wiring applications

V McGahay - Materials, 2010 - mdpi.com
Porous insulators are utilized in the wiring structure of microelectronic devices as a means of
reducing, through low dielectric permittivity, power consumption and signal delay in …

Method of forming a dual damascene structure utilizing a three layer hard mask structure

N Bekiaris, T Weidman, MD Armacost… - US Patent …, 2007 - Google Patents
6,245,662 B1 6, 2001 Naik et al. 6,284,149 B1 9, 2001 Li et al. 6,287,990 B1 9/2001 Cheung
et al. 6,291,334 B1 9, 2001 Somekh 6,303,489 B1 10/2001 Bass 6,303,523 B2 10/2001 …

Quantifying the stress relaxation modulus of polymer thin films via thermal wrinkling

EP Chan, S Kundu, Q Lin… - ACS applied materials & …, 2011 - ACS Publications
The viscoelastic properties of polymer thin films can have a significant impact on the
performance in many small-scale devices. In this work, we use a phenomenon based on a …

Acoustic mirror

R Stoemmer - US Patent 7,230,509, 2007 - Google Patents
An acoustic mirror includes constituent layers that are substantially odd multiples of λ/4. The
constituent layers include a first impedance layer and a second impedance layer, where the …

A 0.13/spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

T Schiml, S Biesemans, G Brase… - 2001 Symposium on …, 2001 - ieeexplore.ieee.org
We describe an advanced 0.13/spl mu/m CMOS technology platform optimized for density,
performance, low power and analog/mixed signal applications. Up to 8 levels of copper …

Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials

SM Gates, JC Hedrick, SV Nitta… - US Patent …, 2004 - Google Patents
(57) ABSTRACT A metal wiring plus low-k dielectric interconnect Structure of the dual
damascene-type is provided wherein the con ductive metal lines and vias are built into a …

Method of forming a dual damascene structure using an amorphous silicon hard mask

T Weidman, N Bekiaris, J Chang… - US Patent 6,806,203, 2004 - Google Patents
US6806203B2 - Method of forming a dual damascene structure using an amorphous silicon
hard mask - Google Patents US6806203B2 - Method of forming a dual damascene structure …

Performance Modeling of Low-/Cu Interconnects for 32-nm-Node and Beyond

M Tada, N Inoue, Y Hayashi - IEEE transactions on electron …, 2009 - ieeexplore.ieee.org
Challenges and issues with the scaling of low-k/Cu interconnects in ultra-large-scale
integration (ULSI) devices are reviewed, and the performance of interconnects is featured by …