This work presents a fractional-ring-oscillator (RO)-based digital phase-locked loop (DPLL).
To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant …

Power consumption is of utmost importance in portable devices as they are operated from a
limited energy supply. Wireless radio is one of the most power-hungry blocks in these …

This article presents a fractional-digital multiplying delay-locked loop (MDLL) that uses a
digital-to-time converter (DTC) for controlling the reference injection timing to support the …

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on
Chip (SoCs) due to their tiny active area and broad tuning range. However, they also …

An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for
space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low …

Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying
delay-locked loops (MDLLs) are promising candidates for low-cost, high-performance clock …

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL)
architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to …

This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled
frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to …

A fractional-N digital phase-locked loop (DPLL) utilizing a cyclic single-delay-pair Vernier
time-to-digital converter (TDC) is introduced. By completely eliminating the quantization step …

As semiconductor fabrication process become complex to achieve target yield and
performance in sub-20nm field-effect transistors (FETs), not only the number of design rule …