Processing-in-memory: A workload-driven perspective

S Ghose, A Boroumand, JS Kim… - IBM Journal of …, 2019 - ieeexplore.ieee.org
Many modern and emerging applications must process increasingly large volumes of data.
Unfortunately, prevalent computing paradigms are not designed to efficiently handle such …

STAMP: Stanford transactional applications for multi-processing

CC Minh, JW Chung, C Kozyrakis… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
Transactional Memory (TM) is emerging as a promising technology to simplify parallel
programming. While several TM systems have been proposed in the research literature, we …

[图书][B] Transactional memory

T Harris, JR Larus, R Rajwar - 2010 - api.taylorfrancis.com
Many of the challenges in building shared-memory data structures stem from needing to
update several memory locations at once—eg, updating four pointers to insert an item into a …

Vantage: Scalable and efficient fine-grain cache partitioning

D Sanchez, C Kozyrakis - Proceedings of the 38th annual international …, 2011 - dl.acm.org
Cache partitioning has a wide range of uses in CMPs, from guaranteeing quality of service
and controlled sharing to security-related techniques. However, existing cache partitioning …

CoNDA: Efficient cache coherence support for near-data accelerators

A Boroumand, S Ghose, M Patel, H Hassan… - Proceedings of the 46th …, 2019 - dl.acm.org
Specialized on-chip accelerators are widely used to improve the energy efficiency of
computing systems. Recent advances in memory technology have enabled near-data …

Software transactional memory: Why is it only a research toy?

C Cascaval, C Blundell, M Michael, HW Cain… - Communications of the …, 2008 - dl.acm.org
Software transactional memory: why is it only a research toy? Page 1 40 communications of the
acm | NovEmbER 2008 | vol. 51 | No. 11 practice trAnsActionAL MEMorY (TM)13 is a …

[图书][B] Transactional memory

JR Larus, R Rajwar - 2022 - books.google.com
The advent of multicore processors has renewed interest in the idea of incorporating
transactions into the programming model used to write parallel programs. This approach …

LogTM-SE: Decoupling hardware transactional memory from caches

L Yen, J Bobba, MR Marty, KE Moore… - 2007 IEEE 13th …, 2007 - ieeexplore.ieee.org
This paper proposes a hardware transactional memory (HTM) system called LogTM
Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transactions read …

The ZCache: Decoupling ways and associativity

D Sanchez, C Kozyrakis - 2010 43rd Annual IEEE/ACM …, 2010 - ieeexplore.ieee.org
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs
towards caches with higher capacity and associativity. Associativity is typically improved by …

An effective hybrid transactional memory system with strong isolation guarantees

CC Minh, M Trautmann, JW Chung… - Proceedings of the 34th …, 2007 - dl.acm.org
We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that
reduces the overhead of software transactions. SigTM uses hardware signatures to track the …