Considerations for ultimate CMOS scaling
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
architectures such as extremely thin silicon-on-insulator and FinFET (and related …
Three-dimensional integrated circuits
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active
devices, have the potential to dramatically enhance chip performance, functionality, and …
devices, have the potential to dramatically enhance chip performance, functionality, and …
A 90-nm logic technology featuring strained-silicon
SE Thompson, M Armstrong, C Auth… - … on electron devices, 2004 - ieeexplore.ieee.org
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length,
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/CDO for high …
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/CDO for high …
A logic nanotechnology featuring strained-silicon
SE Thompson, M Armstrong, C Auth… - IEEE Electron …, 2004 - ieeexplore.ieee.org
Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology. Strained-Si
increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors …
increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors …
TFT-based random access memory cells comprising thyristors
A Bhattacharyya - US Patent 6,812,504, 2004 - Google Patents
The invention includes SOI constructions containing one or more memory cells which
include a transistor and a thyris tor. In one aspect, a scalable GLTRAM cell provides DRAM …
include a transistor and a thyris tor. In one aspect, a scalable GLTRAM cell provides DRAM …
SRAM constructions, and electronic systems comprising SRAM constructions
A Bhattacharyya - US Patent 7,183,611, 2007 - Google Patents
G11C11/41—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using electric elements using semiconductor …
storage elements; Storage elements therefor using electric elements using semiconductor …
Methods of forming transistor constructions
A Bhattacharyya - US Patent 7,291,519, 2007 - Google Patents
US7291519B2 - Methods of forming transistor constructions - Google Patents
US7291519B2 - Methods of forming transistor constructions - Google Patents Methods of …
US7291519B2 - Methods of forming transistor constructions - Google Patents Methods of …
Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing
PR Chidambaram, C Bowen… - … on Electron Devices, 2006 - ieeexplore.ieee.org
Semiconductor industry has increasingly resorted to strain as a means of realizing the
required node-to-node transistor performance improvements. Straining silicon …
required node-to-node transistor performance improvements. Straining silicon …
[图书][B] Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy
JD Cressler, S Monfray, G Freeman, D Friedman… - 2018 - taylorfrancis.com
An extraordinary combination of material science, manufacturing processes, and innovative
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …
In search of" forever," continued transistor scaling one new material at a time
SE Thompson, RS Chau, T Ghani… - IEEE Transactions …, 2005 - ieeexplore.ieee.org
This work looks at past, present, and future material changes for the metal-oxide-
semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk …
semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk …