A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor

S Modanlou, G Ardeshir, M Gholami - Microprocessors and Microsystems, 2023 - Elsevier
This paper presents a time-domain model for general jitter analysis of delay-locked loops
(DLLs). According to this model, the noise contribution of each part of the circuit is specified …

Analysis and design of a low jitter delay‐locked loop using lock state detector

S Modanlou, G Ardeshir… - International Journal of …, 2021 - Wiley Online Library
In this paper, a technique is proposed to improve the jitter performance of a delay‐locked
loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control …

Efficient techniques of fractional-N PLL for pervasive wireless applications

AM Abdul, UR Nelakuditi - International Journal of Pervasive …, 2022 - emerald.com
Purpose The purpose of this paper to ensure the rapid developments in the radio frequency
wireless technology, the synthesis of frequencies for pervasive wireless applications is …

A low power and jitter delay cell with pulse width modulation for wide range delay lock loops

S Modanlou, G Ardeshir, M Gholami - Microelectronics Journal, 2021 - Elsevier
To reach a delay lock loop (DLL) with low jitter and power for wide range frequency
applications, the performance of delay cell used in the voltage-controlled delay line (VCDL) …

Low-Power High-Frequency Phase‎ Frequency Detector Based on Carbon‎ Nano-Tube FET with Zero Dead-Zone for‎ CPPLL

A Shakeri, M Radmehr, A Ghorbani - International Journal of …, 2023 - ijnnonline.net
Achieving low power consumption and low delay are the most important goals that efforts
have been made to reach. In this paper, the process of designing and optimizing the Phase …

Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier

B Srinivasan, P Rajalingam, S Routray - AEU-International Journal of …, 2022 - Elsevier
This paper presents the impact of radiation-induced Single-Event Multiple Transients
(SEMT) in All Digital Delay-Locked Loop (ADDLL) and its impact on the output of frequency …

Employing Parallelization Technique to Reduce Area and Power in a Booth Encoded Algorithm-Based Multiplier

K Javanmardi, S Sofimowloodi, A Attar… - 2024 31st International …, 2024 - ieeexplore.ieee.org
This paper discusses the improvement of the multiplication operation speed in multipliers
based on Booth's algorithm. The main goal of Booth's algorithm is to reduce the number of …

A Wide-Range Delay Lock Loops for Pipelined ADCs

Y Zhai, Z Xiao, T Zhang, S Liang - 2024 6th International …, 2024 - ieeexplore.ieee.org
Traditional clock units, predicated on inverter delay lines, are constrained and often
inadequate for the demands of high-precision analog-to-digital converters (ADCs). This …

[PDF][PDF] WIDE-RANGE LOW-POWER 1.12 PS JITTER DELAY LOCKED LOOP BY A NOVEL LOCK-DETECTION TECHNIQUE

A SHAKERI, M RADMEHR, A GHORBANI - academia.edu
Analog DLLs are formed of a voltage-controlled delay line (VCDL), a phase detector (PD), a
charge pump (CP), and a loop filter. Phase Detector is the main component in designing …