Deepsniffer: A dnn model extraction framework based on learning architectural hints

X Hu, L Liang, S Li, L Deng, P Zuo, Y Ji, X Xie… - Proceedings of the …, 2020 - dl.acm.org
As deep neural networks (DNNs) continue their reach into a wide range of application
domains, the neural network architecture of DNN models becomes an increasingly sensitive …

Neural network model extraction attacks in edge devices by hearing architectural hints

X Hu, L Liang, L Deng, S Li, X Xie, Y Ji, Y Ding… - arXiv preprint arXiv …, 2019 - arxiv.org
As neural networks continue their reach into nearly every aspect of software operations, the
details of those networks become an increasingly sensitive subject. Even those that deploy …

HoPP: Hardware-Software Co-Designed Page Prefetching for Disaggregated Memory

H Li, K Liu, T Liang, Z Li, T Lu, H Yuan… - … Symposium on High …, 2023 - ieeexplore.ieee.org
Memory disaggregation is a promising direction to mitigate memory contention in
datacenters. To make memory disaggregation practical, prior efforts expose remote memory …

[PDF][PDF] mfit: A bump-in-the-wire tool for plug-and-play analysis of rowhammer susceptibility factors

L Cojocar, K Loughlin, S Saroiu… - Technical Report …, 2021 - alecw.azurewebsites.net
Understanding susceptibility to Rowhammer bit flips in DRAM (ie, main memory) is vital to
ensure reliability and security on today's systems, particularly on multitenant cloud servers …

Huffduff: Stealing pruned dnns from sparse accelerators

D Yang, PJ Nair, M Lis - Proceedings of the 28th ACM International …, 2023 - dl.acm.org
Deep learning models are a valuable “secret sauce” that confers a significant competitive
advantage. Many models are never visible to the user and even publicly known state-of-the …

Spindle: Informed memory access monitoring

H Wang, J Zhai, X Tang, B Yu, X Ma… - 2018 USENIX Annual …, 2018 - usenix.org
Memory monitoring is of critical use in understanding applications and evaluating systems.
Due to the dynamic nature in programs' memory accesses, common practice today leaves …

A high-throughput hardware accelerator for lossless compression of a DDR4 command trace

J Choi, B Kim, H Kim, HJ Lee - IEEE Transactions on Very …, 2018 - ieeexplore.ieee.org
In a memory system, understanding how the host is stressing the memory is important to
improve memory performance. Accordingly, the need for the analysis of memory command …

DRAM bandwidth and latency stacks: Visualizing DRAM bottlenecks

S Eyerman, W Heirman, I Hur - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
For memory-bound applications, memory bandwidth utilization and memory access latency
determine performance. DRAM specifications mention the maximum peak bandwidth and …

MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior

H Li, K Liu, T Liang, Z Li, T Lu, Y Chang… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
The virtual memory subsystem (VMS) is a long-standing and integral part of an operating
system (OS). It plays a vital role in enabling remote memory systems over fast data center …

Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory

X Zhang, T Lu, Y Chang, K Zhang… - 2023 IEEE 41st …, 2023 - ieeexplore.ieee.org
Disaggregated memory introduces a cost-effective solution for improving the memory
utilization rate of data centers, by sharing a distributed memory pool among several …