Adiabatic quantum-flux-parametron: A tutorial review

N Takeuchi, T Yamae, CL Ayala, H Suzuki… - IEICE Transactions …, 2022 - search.ieice.org
The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic
element based on the quantum flux parametron. AQFP circuits can operate with energy …

Power-aware computing systems on FPGAs: a survey

G Akgün, M Ali, D Göhringer - 2021 31st International …, 2021 - ieeexplore.ieee.org
A major concern with battery-operated devices is power-awareness and its appropriate
computing. The power dissipation of such systems is usually considered a hardware …

KAPow: High-accuracy, low-overhead online per-module power estimation for FPGA designs

JJ Davis, E Hung, JM Levine, EA Stott… - ACM Transactions on …, 2018 - dl.acm.org
In an FPGA system-on-chip design, it is often insufficient to merely assess the power
consumption of the entire circuit by compile-time estimation or runtime power measurement …

Decision tree based hardware power monitoring for run time dynamic power management in FPGA

Z Lin, W Zhang, S Sharad - 2017 27th International Conference …, 2017 - ieeexplore.ieee.org
Fine-grained runtime power management techniques could be promising solutions for
power reduction. Therefore, it is essential to establish accurate power monitoring schemes …

Guac: Energy-Aware and SSA-Based Generation of Coarse-Grained Merged Accelerators from LLVM-IR

I Brumar, R Rocha, A Bernat, D Tripathy… - arXiv preprint arXiv …, 2024 - arxiv.org
Designing accelerators for resource-and power-constrained applications is a daunting task.
High-level Synthesis (HLS) addresses these constraints through resource sharing, an …

Power modeling on FPGA: A neural model for RT-level power estimation

Y Nasser, JC Prévotet, M Hélard - Proceedings of the 15th ACM …, 2018 - dl.acm.org
Today reducing power consumption is a major concern especially when it concerns small
embedded devices. Power optimization is required all along the design flow but particularly …

Dynamic energy management of fpga accelerators in embedded systems

M Hosseinabady, JL Nunez-Yanez - ACM Transactions on Embedded …, 2018 - dl.acm.org
In this article, we investigate how to utilise an Field-Programmable Gate Array (FPGA) in an
embedded system to save energy. For this purpose, we study the energy efficiency of a …

Can approximate computing reduce power consumption on FPGAs?

J Echavarria, K Schütz, A Becher… - 2018 25th IEEE …, 2018 - ieeexplore.ieee.org
Approximate computing allows tackling conflicting objectives, such as power and accuracy
of computations. In this paper, we first describe how knowledge of stimuli's specific features …

Early-Stage Non-Conventional Hardware Accelerator Discovery via Optimization Methods and Compiler Analysis

I Brumar - 2023 - search.proquest.com
In the post-Moore era, where we witness the diminishing returns of traditional transistor
scaling, a pivotal transition in accelerator design methodologies has been necessitated to …

KOCL: Power self-awareness for arbitrary FPGA-SoC-accelerated OpenCL applications

JJ Davis, JM Levine, EA Stott, E Hung… - IEEE Design & …, 2017 - ieeexplore.ieee.org
Being aware of its own power consumption is essential for any system under power
constraints, ie all systems with moderate or high complexity. This paper describes a tool that …