Stacked semiconductor apparatus with configurable vertical I/O
H ju CHUNG, JB Lee, H Lee - US Patent 7,990,171, 2011 - Google Patents
US7990171B2 - Stacked semiconductor apparatus with configurable vertical I/O - Google
Patents US7990171B2 - Stacked semiconductor apparatus with configurable vertical I/O …
Patents US7990171B2 - Stacked semiconductor apparatus with configurable vertical I/O …
Stack position determination in memory devices configured for stacked arrangements
MC Stephens Jr - US Patent 9,218,854, 2015 - Google Patents
Disclosed are various embodiments related to stacked memory devices, such as DRAMs,
SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned …
SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned …
Semiconductor device
C Kondo - US Patent App. 13/317,167, 2012 - Google Patents
G11C11/401—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using electric elements using semiconductor …
storage elements; Storage elements therefor using electric elements using semiconductor …
Multi-function information handling system with multi-orientation stand
JT Morrison, S Kamepalli - US Patent 9,229,477, 2016 - Google Patents
A tablet information handling system processes information with processing components
disposed in a planar housing for presentation as images at a display disposed at the upper …
disposed in a planar housing for presentation as images at a display disposed at the upper …
Semiconductor device having plural memory chip
A Ide - US Patent 9,252,081, 2016 - Google Patents
A semiconductor device includes a stacked plurality of memory chips. The memory chips
each include a plurality of memory banks, a plurality of read/write buses that are assigned to …
each include a plurality of memory banks, a plurality of read/write buses that are assigned to …
Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements
MC Stephens Jr - US Patent 9,153,298, 2015 - Google Patents
Disclosed are various embodiments related to stacked memory devices, such as DRAMs,
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are …
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are …
Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
MC Stephens Jr - US Patent 9,659,628, 2017 - Google Patents
Disclosed are various embodiments related to stacked memory devices, such as DRAMs,
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifi ers (SPIDs) …
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifi ers (SPIDs) …
Memory devices with serially connected signals for stacked arrangements
MC Stephens Jr - US Patent 9,183,891, 2015 - Google Patents
(Continued) Primary Examiner—Son Dinh (57) ABSTRACT Disclosed are various
embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and …
embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and …
Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements
MC Stephens Jr - US Patent 9,153,299, 2015 - Google Patents
Disclosed are various embodiments related to stacked memory devices, such as DRAMs,
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are …
SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are …
Stacked semiconductor apparatus with configurable vertical I/O
H ju CHUNG, JB Lee, H Lee - US Patent 8,736,296, 2014 - Google Patents
The present invention provides an apparatus including a stacked plurality of devices and a
related method. The appa ratus includes a stacked plurality of devices including a mas ter …
related method. The appa ratus includes a stacked plurality of devices including a mas ter …