Enabling exact delay synthesis
Given (i) a Boolean function,(ii) a set of arrival times at the inputs, and (iii) a gate library with
associated delay values, the exact delay synthesis problem asks for a circuit implementation …
associated delay values, the exact delay synthesis problem asks for a circuit implementation …
Unlocking fine-grain parallelism for AIG rewriting
Parallel computing is a trend to enhance scalability of electronic design automation (EDA)
tools using widely available multicore platforms. In order to benefit from parallelism, well …
tools using widely available multicore platforms. In order to benefit from parallelism, well …
A Recursion and Lock Free GPU-based Logic Rewriting Framework Exploiting Both Intra-node and Inter-node Parallelism
L Li, R Li, Y Ha - IEEE Transactions on Computer-Aided Design …, 2023 - ieeexplore.ieee.org
Logic rewriting is an effective but time-consuming technique to optimize the multilevel logic
network by rewriting subnetworks of the input network with other logic equivalent structures …
network by rewriting subnetworks of the input network with other logic equivalent structures …
Physical awareness starting at technology-independent logic synthesis
This chapter presents a reflection on a VLSI design flow better suited to integrate logic
synthesis and physical design. Historically, VLSI design flows were a sequence of relatively …
synthesis and physical design. Historically, VLSI design flows were a sequence of relatively …
Novel sat-based invariant-directed low-power synthesis
M Elbayoumi, MS Hsiao… - … Symposium on Quality …, 2015 - ieeexplore.ieee.org
Dynamic power consumption is a critical concern in the design of both high performance
and low-power circuits. Clock-gating is one of the most efficient and prominent approaches …
and low-power circuits. Clock-gating is one of the most efficient and prominent approaches …
Bridging high performance and low power in processor design
The design complexity of modern high performance processors calls for innovative design
techniques and methodologies for achieving time-to-market goals. New design techniques …
techniques and methodologies for achieving time-to-market goals. New design techniques …
[PDF][PDF] Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
MAMS Elbayoumi - 2015 - vtechworks.lib.vt.edu
According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This
causes an exponential increase of the available area, and hence, the complexity of modern …
causes an exponential increase of the available area, and hence, the complexity of modern …
Strategies for Quality and Performance Improvement of Hardware Verification and Synthesis Algorithms
MAMS Elbayoumi - 2014 - search.proquest.com
According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This
causes an exponential increase of the available area, and hence, the complexity of modern …
causes an exponential increase of the available area, and hence, the complexity of modern …