Using control flow data structures to direct and track instruction execution
J Bobba, R Sasanka, JJ Cook, A Das… - US Patent …, 2018 - Google Patents
A mechanism for tracking the control flow of instructions in an application and performing
one or more optimizations of a processing device, based on the control flow of the …
one or more optimizations of a processing device, based on the control flow of the …
An approach for compiler optimization to exploit instruction level parallelism
Abstract Instruction Level Parallelism (ILP) is not the new idea. Unfortunately ILP
architecture not well suited to for all conventional high level language compilers and …
architecture not well suited to for all conventional high level language compilers and …
[PDF][PDF] INSTRUCTION LEVEL PARALLELISM–THE ROLE OF ARCHITECTURE AND COMPILER
The instruction level parallelism (ILP) is not a new idea. It has been in practice since 1970
and became a much more significant force in computer design by 1980s. The researchers …
and became a much more significant force in computer design by 1980s. The researchers …
A novel heuristic for selection of hyperblock in If-conversion
In this paper we present a novel heuristic for selection of hyperblock in If-conversion. The if-
conversion has been applied to be promising method for exploitation of ILP in the presence …
conversion has been applied to be promising method for exploitation of ILP in the presence …
[PDF][PDF] ILP Exploitation and Speedup Issues and Their Solutions through Balanced Scheduling
In this paper, we present issues associated with hardware and compiler to exploit instruction
level parallelism. In this reference the solutions related to balanced scheduling have been …
level parallelism. In this reference the solutions related to balanced scheduling have been …