Public cloud providers seek to meet stringent performance requirements and low hardware
cost. A key driver of performance and cost is main memory. Memory pooling promises to …

Hardware Performance Counters (HPCs) have been available in processors for more than a
decade. These counters can be used to monitor and measure events that occur at the CPU …

In a multicore system, effective management of shared last level cache (LLC), such as
hardware/software cache partitioning, has attracted significant research attention. Some …

Memory-bound stalls account for a significant portion of CPU cycles in datacenter
workloads, which makes harvesting them to execute other useful work highly valuable …

Non Uniform Memory Access (NUMA) architectures are nowadays common for running High-
Performance Computing (HPC) applications. In such architectures, several distinct physical …

Dataflow graphs are a popular abstraction for describing computation, used in many
systems for high-level optimization. For execution, dataflow graphs are lowered and …

Many performance studies rely on Intel's Precise Event Based Sampling (PEBS) to collect
processor events, where precision is a key for the reliability of analysis. In this paper, we …

Precise event sampling is a profiling feature in commodity processors that can sample
hardware events and accurately locate the instructions that trigger the events. This feature …

Main memory dominates data center server cost, and hence data center operators are
exploring alternative technologies such as CXL-attached and persistent memory to improve …

This paper presents Specularizer, a framework for uncovering speculative execution attacks
using performance tracing features available in commodity processors. It is motivated by the …