A survey of techniques for reducing interference in real-time applications on multicore platforms

T Lugo, S Lozano, J Fernández, J Carretero - IEEE Access, 2022 - ieeexplore.ieee.org
This survey reviews the scientific literature on techniques for reducing interference in real-
time multicore systems, focusing on the approaches proposed between 2015 and 2020. It …

A systematic approach to achieving tight worst-case latency and high-performance under predictable cache coherence

AM Kaushik, H Patel - 2021 IEEE 27th Real-Time and …, 2021 - ieeexplore.ieee.org
Predictable hardware cache coherence is an attractive data communication mechanism
between safety-critical tasks deployed on real-time multi-core platforms due to its …

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems

S Hessien, M Hassan - ACM Transactions on Embedded Computing …, 2022 - dl.acm.org
Tasks in modern embedded systems such as automotive and avionics communicate among
each other using shared data towards achieving the desired functionality of the whole …

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources

S Abdelhalim, D Germchi, M Hossam… - … Conference on Real …, 2023 - drops.dagstuhl.de
To facilitate the safe adoption of multi-core platforms in real-time systems, a plethora of
recent research efforts aim at bounding the delays induced by interference upon accessing …

[PDF][PDF] Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds

R Mirosanlou, M Hassan… - … Euromicro Conference on …, 2022 - drops.dagstuhl.de
Abstract In Commercial-Off-The-Shelf (COTS) systems-on-chip, processing elements
communicate data through a shared memory hierarchy, and a coherent high-performance …

Predictably and efficiently integrating cots cache coherence in real-time systems

M Hossam, M Hassan - … on Real-Time Systems (ECRTS 2022), 2022 - drops.dagstuhl.de
The adoption of multi-core platforms in embedded real-time systems mandates predictable
system components. Such components must guarantee the satisfaction of the timing …

Disco: Time-compositional cache coherence for multi-core real-time embedded systems

M Hassan - IEEE Transactions on Computers, 2022 - ieeexplore.ieee.org
Tasks in modern embedded systems share data and communicate among each other.
Nonetheless, the majority of research in real-time systems either assumes that tasks do not …

Comparative analysis of simulators for optical network-on-chip (ONoC)

H Zhang, Y Chen, Z Huang, C Xia… - 2021 12th …, 2021 - ieeexplore.ieee.org
On-chip optical interconnection technology can provide faster transmission speed, greater
communication bandwidth and higher energy efficiency, which has been proposed to …

D-wash–A dynamic workload aware adaptive cache coherance protocol for multi-core processor system

V Uma, R Marimuthu - Microelectronics Journal, 2023 - Elsevier
In today's world, multi-processor plays the vital role in designing supercomputer, mobile
phones and other wearable embedded systems. To handle power and latency issues in …

SwiftDir: Secure cache coherence without overprotection

C Miao, K Bu, M Li, S Mao, J Jia - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Cache coherence states have recently been exploited to leak secrets through timing-
channel attacks. The root cause lies in the fact that shared data in state Exclusive (E) and …