A 23-mW 24-GS/s 6-bit voltage-time hybrid time-interleaved ADC in 28-nm CMOS
This paper presents a power-and area-efficient 16-way time-interleaved (TI) analog-to-
digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm …
digital converter (ADC) achieving 24-GS/s conversion speed and 6-bit resolution in 28-nm …
CMOS ADC-based receivers for high-speed electrical and optical links
CMOS ADC-based serial link receivers enable powerful digital equalization and symbol
detection techniques for high data rate operation over electrical and optical wireline …
detection techniques for high data rate operation over electrical and optical wireline …
A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS
MQ Le, J Gorecki, J Riani, J Pernillo… - 2017 IEEE Custom …, 2017 - ieeexplore.ieee.org
A 28-GS/s time-interleaved ADC suitable for PAM4 optical and backplane applications is
presented. The architecture uses a two-rank 2×(4: 4) sampling network to interleave 32 8b …
presented. The architecture uses a two-rank 2×(4: 4) sampling network to interleave 32 8b …
A 40-nm CMOS 7-b 32-GS/s SAR ADC with background channel mismatch calibration
This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital
converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi …
converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi …
A 10 Gb/s hybrid ADC-based receiver with embedded analog and per-symbol dynamically enabled digital equalization
While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital
equalization for high data rate operation, the ADC and digital equalization power …
equalization for high data rate operation, the ADC and digital equalization power …
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE
A PAM-4 ADC-based receiver employs a 32-way time-interleaved 6-bit 2-bit/stage loop-
unrolled SAR ADC with a single capacitive reference DAC. Digital equalization complexity is …
unrolled SAR ADC with a single capacitive reference DAC. Digital equalization complexity is …
A 25 GS/s 6b TI two-stage multi-bit search ADC with soft-decision selection algorithm in 65 nm CMOS
While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable
flexible and powerful digital signal processing-based (DSP-based) equalization, the …
flexible and powerful digital signal processing-based (DSP-based) equalization, the …
Analog to sequence converter-based PAM-4 receiver with built-in error correction
M Mohammad, M Hossain - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
This paper describes an energy-efficient pulse-amplitude modulation (PAM)-4 digital
receiver based on sequence detection. The proposed scheme exploits the pre-cursor ISI in …
receiver based on sequence detection. The proposed scheme exploits the pre-cursor ISI in …
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators
While resistive random-access memory (ReRAM) crossbar arrays have the potential to
significantly accelerate deep neural network (DNN) training through fast and low-cost matrix …
significantly accelerate deep neural network (DNN) training through fast and low-cost matrix …
3.125 GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
S Serunjogi, M Sanduleanu - 2023 IFIP/IEEE 31st International …, 2023 - ieeexplore.ieee.org
This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay
Line and Time to Digital Converter. The design is operating at 3.125 GS/s with 4.9 ENOB …
Line and Time to Digital Converter. The design is operating at 3.125 GS/s with 4.9 ENOB …