A large variety of printing, deposition and writing techniques have been incorporated to
fabricate electronic devices in the last decades. This approach, printed electronics, has …

The main aim of this work is to study the effect of symmetric and asymmetric spacer length
variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire …

In this paper, a 2D analytical potential model for n+ SiGe Gate stacked linearly graded work
function Vertical TFET (n+ SiGe GS-LGW-VTFET) is developed with incorporating the effect …

The growing demand for miniaturized transistors with increased performance and low power
consumption has scaled down the device to the nanoscale regime. The design and …

Ultra-efficient fundamental fuzzy Min and Max circuits are proposed in this paper using 3
CNTFETs. These are much energy-efficient compared to the state-of-the-art previous …

We propose a numerical compact model for describing the drain current in ballistic mode by
using an expression to represent the transmission coefficients for all operating regions. This …

To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT
JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration …

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their
superior channel control capability and short channel effect (SCE) resistance. To achieve …

The impact of the work function modulation (WFM) in sub-20nm strained silicon channel
double gate (SSCDG) junctionless transistor (JLT) is explored in this article for low power …

Abstract This paper presents Gate Stacked junctionless nanotube gate all around MOSFET
(GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS …