A new parallel SystemC kernel leveraging manycore architectures
N Ventroux, T Sassolas - 2016 Design, Automation & Test in …, 2016 - ieeexplore.ieee.org
The complexity of system-level modeling is continuously increasing. Electronic System Level
(ESL) design requires fast simulation techniques to control future SoC development cost and …
(ESL) design requires fast simulation techniques to control future SoC development cost and …
Parallel SystemC simulation for ESL design
JH Weinstock, LG Murillo, R Leupers… - ACM Transactions on …, 2016 - dl.acm.org
Virtual platforms have become essential tools for the design of embedded systems.
Developers rely on them for design space exploration and software debugging. However …
Developers rely on them for design space exploration and software debugging. However …
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations
The complexity of SystemC virtual prototyping is continuously increasing. Accelerating
RTL/TLM SystemC simulations is essential to control future SoC development cost and time …
RTL/TLM SystemC simulations is essential to control future SoC development cost and time …
Challenges for the parallelization of loosely timed SystemC programs
D Becker, M Moy, J Cornet - 2015 International Symposium on …, 2015 - ieeexplore.ieee.org
SystemC/TLM models are commonly used in the industry to provide an early SoC simulation
environment. The open source implementation of the SystemC simulator is sequential. The …
environment. The open source implementation of the SystemC simulator is sequential. The …
Distributed, loosely-synchronized SystemC/TLM simulations of many-processor platforms
C Sauer, HM Bluethgen… - Proceedings of the 2014 …, 2014 - ieeexplore.ieee.org
Today's virtual prototypes model complex manycore platforms. In application domains such
as network processing, they may comprise hundreds of processors, which makes simulation …
as network processing, they may comprise hundreds of processors, which makes simulation …
Parallel simulation of loosely timed systemC/TLM programs: challenges raised by an industrial case study
D Becker, M Moy, J Cornet - Electronics, 2016 - mdpi.com
Transaction level models of systems-on-chip in SystemC are commonly used in the industry
to provide an early simulation environment. The SystemC standard imposes coroutine …
to provide an early simulation environment. The SystemC standard imposes coroutine …
Hierarchical simulation of onboard networks
V Olenev, I Lavrovskaya, I Korobkov, N Sinyov… - Intelligent Distributed …, 2020 - Springer
The paper presents a solution for hierarchical simulation of onboard networks, which allows
performing simulation at different levels of details. This solution was integrated into a new …
performing simulation at different levels of details. This solution was integrated into a new …
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures
Within this article an adaptive approach for parallel simulation of SystemC RTL models on
future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is …
future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is …
X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
The complexity of modern heterogeneous systems leads to simulation performance
problems. We show how heterogeneous system verification can be accelerated using a …
problems. We show how heterogeneous system verification can be accelerated using a …
A comparison of parallel systemc simulation approaches at RTL
B Haetzer, M Radetzki - Proceedings of the 2014 Forum on …, 2014 - ieeexplore.ieee.org
This paper presents a holistic comparison of different parallel SystemC simulation
approaches at the register transfer level (RTL). The effect of RTL modeling styles and …
approaches at the register transfer level (RTL). The effect of RTL modeling styles and …