In this paper we present theory and experimental results on Algebraic Decision Diagrams.
These diagrams extend BDDs by allowing values from an arbitrary finite domain to be …

In two editions spanning more than a decade, The Electrical Engineering Handbook stands
as the definitive reference to the multidisciplinary field of electrical engineering. Our …

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is
modified to represent state graphs using binary decision diagrams (BDD's) and partitioned …

Hardware description languages (HDLs) dramatically change the way circuit designers
work. These languages can be used to describe circuits at a very high level of abstraction …

Formal Equivalence Checking and Design Debugging covers two major topics in design
verification: logic equivalence checking and design debugging. The first part of the book …

We present a method of automatic generation of functional vectors for sequential circuits.
These vectors can be used for design verification, manufacturing testing, or power …

We address the problem of reachability analysis for large finite state systems. Symbolic
techniques have revolutionized reachability analysis but still have limitations in traversing …

Regarding finite state machines as Markov chains facilitates the application of probabilistic
methods to very large logic synthesis and formal verification problems. In this paper we …

Traditional ROBDD-based methods of automated verification suffer from the drawback that
they require a binary representation of the circuit. To overcome this limitation we propose a …

A system for specifying, synthesizing, analyzing, simulating, and generating circuit designs
for frame protocols. A GUI allows a user to specify a frame protocol and to edit and browse …