LUTNet: Rethinking inference in FPGA soft logic

E Wang, JJ Davis, PYK Cheung… - 2019 IEEE 27th …, 2019 - ieeexplore.ieee.org
Research has shown that deep neural networks contain significant redundancy, and that
high classification accuracies can be achieved even when weights and activations are …

High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks

RS Molina, V Gil-Costa, ML Crespo, G Ramponi - IEEE Access, 2022 - ieeexplore.ieee.org
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …

LUTNet: Learning FPGA configurations for highly efficient neural network inference

E Wang, JJ Davis, PYK Cheung… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Research has shown that deep neural networks contain significant redundancy, and thus
that high classification accuracy can be achieved even when weights and activations are …

RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey

Y Nasser, J Lorandel, JC Prévotet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …

Hl-pow: learning-assisted pre-RTL power modeling and optimization for FPGA HLS

Z Lin, T Liang, J Zhao, S Sinha… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
High-level synthesis (HLS) enables designers to customize hardware designs without the
need for delving into low-level hardware details. However, it is still challenging to establish …

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power

Z Lin, S Sinha, W Zhang - IEEE Transactions on Computer …, 2018 - ieeexplore.ieee.org
As field-programmable gate arrays (FPGAs) become prevalent in critical application
domains, their power consumption is of high concern. In this paper, we present and evaluate …

High-level early power estimation of FPGA IP based on machine learning

M Richa, JC Prévotet, M Dardaillon… - 2022 29th IEEE …, 2022 - ieeexplore.ieee.org
When high speed and high performance are key features of a specific FPGA-based system,
increase in energy consumption becomes the main hurdle to be tackled while keeping a …

Power Consumption Modeling in Embedded Systems Hardware

M Richa - 2023 - theses.hal.science
Power optimization has become a major concern for most digital hardware designers,
particularly in early design phases and especially in limited power budget systems (battery …

High-Level Online Power Monitoring of FPGA IP Based on Machine Learning

M Richa, JC Prévotet, M Dardaillon, M Mroué… - … Workshop on Design …, 2023 - Springer
Nowadays, power optimization has become a major interest for most digital hardware
designers. Some, traditionally, might stick to offline power estimation especially in early …

SoC-based FPGA architecture for image analysis and other highly demanding applications

RS Molina - 2023 - arts.units.it
Nowadays, the development of algorithms focuses on performance-efficient and energy-
efficient computations. Technologies such as field programmable gate array (FPGA) and …