A survey on biometric cryptosystems and their applications
S Sharma, A Saini, S Chaudhury - Computers & Security, 2023 - Elsevier
Biometric systems (BSs) have shown prominent results in providing secure authentication
protocols and a unique identification ecosystem for various applications. Over the years …
protocols and a unique identification ecosystem for various applications. Over the years …
340 mv–1.1 v, 289 gbps/w, 2090-gate nanoaes hardware accelerator with area-optimized encrypt/decrypt gf (2 4) 2 polynomials in 22 nm tri-gate cmos
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22
nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption …
nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption …
AES-Based Security Coprocessor IC in 0.18-$ muhbox m $ CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by
monitoring the power consumption or other information that is leaked by the switching …
monitoring the power consumption or other information that is leaked by the switching …
A digital design flow for secure integrated circuits
K Tiri, I Verbauwhede - … Aided Design of Integrated Circuits and …, 2006 - ieeexplore.ieee.org
Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called
side-channel attacks (SCAs). The attacker can gain information by monitoring the power …
side-channel attacks (SCAs). The attacker can gain information by monitoring the power …
53 Gbps Native Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
SK Mathew, F Sheikh, M Kounavis… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator
fabricated in 45 nm CMOS, targeted for content-protection in high-performance …
fabricated in 45 nm CMOS, targeted for content-protection in high-performance …
Side-channel attack pitfalls
K Tiri - Proceedings of the 44th annual Design Automation …, 2007 - dl.acm.org
While cryptographic algorithms are usually strong against mathematical attacks, their
practical implementation, both in software and in hardware, opens the door to side-channel …
practical implementation, both in software and in hardware, opens the door to side-channel …
Chaotic clock driven cryptographic chip: Towards a DPA resistant AES processor
Designing a tamper-resistant microchip for small embedded systems is one of the urgent
demands of the computing community nowadays due to the immense security challenges …
demands of the computing community nowadays due to the immense security challenges …
Reconfigurable system for high-speed and diversified AES using FPGA
MH Jing, ZH Chen, JH Chen, YH Chen - Microprocessors and …, 2007 - Elsevier
In this article, we present a FPGA-based reconfigurable system for the advanced encryption
standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the …
standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the …
Energy-efficient and secure s-box circuit using symmetric pass gate adiabatic logic
SD Kumar, H Thapliyal, A Mohammad… - 2016 IEEE Computer …, 2016 - ieeexplore.ieee.org
Differential Power Analysis (DPA) attack is considered to be a main threat while designing
cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to …
cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to …