Provided are a semiconductor device, which can facilitate a salicide process and can
prevent a gate from being damaged due to misalign, and a method of manufacturing of the …

A process for conformally doping through the vertical and horizontal surfaces of a 3-
dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF …

0001. This application claims the benefit of US Provi sional Application No. 61/247,300, filed
Sep. 30, 2009, the disclosure of which is incorporated by reference herein. This application …

6,808 004 B2 10/2004 Kamm et a1, 7,398,497 B2 7/2008 Sato et 31. 63083994 B1 10/2004
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …

Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …

The present invention facilitates semiconductor device fabri cation by providing mechanisms
for utilizing different isola tion schemes within embedded memory and other logic por tions …

A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a
semiconductor workpiece, is carried out by maintaining the workpiece at an elevated …

An advanced transistor with punch through suppression includes a gate with length Lg, a
well doped to have a? rst concentration of a dopant, and a screening region positioned …

US7294556B2 - Method of forming trench isolation in the fabrication of integrated circuitry -
Google Patents US7294556B2 - Method of forming trench isolation in the fabrication of …

5,144,378 5,156,989 5,156,990 5,166,765 5,208.473 5,294,821 5,298.763 5,369,288 5,373,
186 5,384,476 5,426.328 5,444,008 5,552,332 5,559,368 5,608,253 5,622,880 5,624,863 …