[图书][B] Embedded system design: embedded systems foundations of cyber-physical systems, and the internet of things

P Marwedel - 2021 - library.oapen.org
A unique feature of this open access textbook is to provide a comprehensive introduction to
the fundamental knowledge in embedded systems, with applications in cyber-physical …

[图书][B] Eingebettete Systeme: Grundlagen Eingebetteter Systeme in Cyber-Physikalischen Systemen

P Marwedel - 2021 - library.oapen.org
Abstract Ein Alleinstellungsmerkmal dieses Open-Access-Lehrbuchs ist die umfassende
Einführung in das Grundlagenwissen über eingebettete Systeme mit Anwendungen in cyber …

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

C Qi, L Xiao, J Guo, T Wang - Microelectronics reliability, 2015 - Elsevier
As a consequence of technology scaling down, gate capacitances and stored charge in
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …

A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

IC Wey, YS Yang, BC Wu, CC Peng - Microelectronics Journal, 2014 - Elsevier
Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit
designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by …

[HTML][HTML] RHBD techniques to mitigate SEU and SET in CMOS frequency synthesizers

V Díez-Acereda, S L. Khemchandani, J Del Pino… - Electronics, 2019 - mdpi.com
This paper presents a thorough study of radiation effects on a frequency synthesizer
designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy …

Static delay variation models for ripple-carry and borrow-save adders

K Papachatzopoulos, V Paliouras - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper introduces two statistical delay-variability models for certain hardware adder
implementations, namely, the ripple-carry adder (RCA) and the borrow-save adder (BSA) …

TCAD simulation of the 65-nm CMOS logical elements of the decoders with single-event transients compensation

YV Katunin, VY Stenin - 2018 Moscow Workshop on Electronic …, 2018 - ieeexplore.ieee.org
Logical elements with single-event compensations were designed and simulated on the
bulk 65-nm CMOS design rule. The effects of single-event transients under impacts of single …

[PDF][PDF] Translation lookaside buffer on the 65-nm STG DICE hardened elements

VY Stenin, AV Antonyuk, YV Katunin, PV Stepanov - Telfor Journal, 2018 - journal.telfor.rs
This paper presents the design of hardened translation lookaside buffer based on Spaced
Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to …

Towards brain-inspired computing

Z Gingl, LB Kish, SP Khatri - Fluctuation and Noise Letters, 2010 - World Scientific
We present introductory considerations and analysis toward computing applications based
on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys …

TCAD моделирование эффектов воздействия одиночных ядерных частиц на ячейки памяти STG DICE

ЮВ Катунин, ВЯ Стенин - Микроэлектроника, 2018 - elibrary.ru
TCAD моделирование воздействий одиночных ядерных частиц на ячейки памяти STG
DICE с транзисторами, разнесенными на две группы (Spaced Transistor Groups DICE) …