Abstract Ein Alleinstellungsmerkmal dieses Open-Access-Lehrbuchs ist die umfassende Einführung in das Grundlagenwissen über eingebettete Systeme mit Anwendungen in cyber …
C Qi, L Xiao, J Guo, T Wang - Microelectronics reliability, 2015 - Elsevier
As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
IC Wey, YS Yang, BC Wu, CC Peng - Microelectronics Journal, 2014 - Elsevier
Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by …
V Díez-Acereda, S L. Khemchandani, J Del Pino… - Electronics, 2019 - mdpi.com
This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy …
K Papachatzopoulos, V Paliouras - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper introduces two statistical delay-variability models for certain hardware adder implementations, namely, the ripple-carry adder (RCA) and the borrow-save adder (BSA) …
Logical elements with single-event compensations were designed and simulated on the bulk 65-nm CMOS design rule. The effects of single-event transients under impacts of single …
This paper presents the design of hardened translation lookaside buffer based on Spaced Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to …
We present introductory considerations and analysis toward computing applications based on the recently introduced deterministic logic scheme with random spike (pulse) trains [Phys …
TCAD моделирование воздействий одиночных ядерных частиц на ячейки памяти STG DICE с транзисторами, разнесенными на две группы (Spaced Transistor Groups DICE) …