Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL
T Jauch, A Wezel, MR Fadiheh… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
Spectre and Meltdown attacks proved Transient Execution Side Channels to be a notable
challenge for designing secure microarchitectures. Various countermeasures against these …
challenge for designing secure microarchitectures. Various countermeasures against these …
PORTAL: Fast and Secure Device Access with Arm CCA for Modern Arm Mobile System-on-Chips (SoCs)
The increasing integration of diverse co-processors and peripherals within mobile Arm
System-on-Chips (SoCs) presents significant challenges for secure and efficient device I/O …
System-on-Chips (SoCs) presents significant challenges for secure and efficient device I/O …
DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement
Modern System-on-Chip (SoC) designs that rely on bus architectures are susceptible to a
range of hardware and software threats, necessitating the implementation of diverse security …
range of hardware and software threats, necessitating the implementation of diverse security …
MCU-Wide Timing Side Channels and Their Detection
J Müller, AL Duque Antón, L Deutschmann… - Proceedings of the 61st …, 2024 - dl.acm.org
Microarchitectural timing side channels have been thoroughly investigated as a security
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …
A New Security Threat in MCUs--SoC-wide timing side channels and how to find them
Microarchitectural timing side channels have been thoroughly investigated as a security
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …
threat in hardware designs featuring shared buffers (eg, caches) and/or parallelism between …
[PDF][PDF] Hardening and Adapting Trusted Execution Environments for Emerging Platforms
F Sang - 2024 - gts3.org
HARDENING AND ADAPTING TRUSTED EXECUTION ENVIRONMENTS FOR EMERGING
PLATFORMS A Dissertation Presented to The Academic Faculty By Page 1 HARDENING AND …
PLATFORMS A Dissertation Presented to The Academic Faculty By Page 1 HARDENING AND …
[PDF][PDF] eXpect: On the Security Implications of Violations in AXI Implementations
M Zonta-Roudes, A Meza, N Hinderling… - 2024 - n.ethz.ch
The Arm Advanced eXtensible Interface (AXI) protocol is a specification for system-on-chip
(SoC) communication [14]. It consists of interfaces such as AXI-Lite and AXI-Full and is a part …
(SoC) communication [14]. It consists of interfaces such as AXI-Lite and AXI-Full and is a part …