Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered...

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

M Parvathi, N Vasantha… - International Journal of …, 2018 - search.proquest.com
One of the important block of BIST controller is LFSR and the speed with which BIST
operates depends on LFSR systems design. There are methods in implementing LFSR …
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[PDF][PDF] BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications

M Parvathi, N Vasantha, KS Prasad - 2018 - academia.edu
One of the important block of BIST controller is LFSR and the speed with which BIST
operates depends on LFSR systems design. There are methods in implementing LFSR …
相关文章