Hardware execution driven application level derating calculation for soft error rate analysis
Mechanisms are provided for predicting effects of soft errors on an integrated circuit device
design. A data processing system is con? gured to implement a uni? ed derating tool that …
design. A data processing system is con? gured to implement a uni? ed derating tool that …
Modeling system-level effects of soft errors
P Bose, PN Kudva, JA Rivers, PN Sanda… - US Patent …, 2012 - Google Patents
2. Background of the Invention As technological trends head toward Smaller devices and
wire dimensions, system design is entering an era of increased chip integration, reduced …
wire dimensions, system design is entering an era of increased chip integration, reduced …
On failure rate assessment using an executable model of the system
MH Neishaburi, Z Zilic - 2011 14th Euromicro Conference on …, 2011 - ieeexplore.ieee.org
Statistical data from many application fields confirm that SoC products implemented in
modern deep submicron technologies are getting more and more susceptible to transient …
modern deep submicron technologies are getting more and more susceptible to transient …
System on chip failure rate assessment using the executable model of a system
MH Neishaburi, Z Zilic - Computing, 2015 - Springer
Statistical data from many application fields confirm that System on Chips (SoCs) products
implemented in modern deep submicron technologies are getting more and more sensitive …
implemented in modern deep submicron technologies are getting more and more sensitive …