Logic synthesis is an enabling technology to realize integrated computing systems, and it
entails solving computationally intractable problems through a plurality of heuristic …

We present a synthesis framework to map logic networks into quantum circuits for quantum
computing. The synthesis framework is based on lookup-table (LUT) networks, which play a …

Most existing technology mapping algorithms use graph covering approaches and suffer
from the netlist structural bias problem. Chen and Cong proposed a simultaneous simple …

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to
map combinational logic into lookup tables (LUTs) structures when synthesizing hardware …

Given (i) a Boolean function,(ii) a set of arrival times at the inputs, and (iii) a gate library with
associated delay values, the exact delay synthesis problem asks for a circuit implementation …

Quantum compilation is the task of translating a quantum algorithm implemented in a high-
level quantum programming language into a technology-dependent instructions flow for a …

We present a synthesis framework to map logic networks into quantum circuits for quantum
computing. The synthesis framework is based on LUT networks (lookup-table networks) …

Modern FPGA synthesis tools typically apply a predetermined sequence of logic
optimizations on the input logic network before carrying out technology mapping. While the …

This paper addresses the challenge of reducing the number of nodes in Look-Up Table
(LUT) networks with two significant applications. First, Field-Programmable Gate Arrays …

In recent times, Bounded Model Checking (BMC) engines have gained wide prominence in
formal verification. Different BMC engines exist, differing in their optimization …