Automated, retargetable back-annotation for host compiled performance and power modeling

S Chakravarty, Z Zhao… - … Conference on Hardware …, 2013 - ieeexplore.ieee.org
With traditional cycle-accurate or instruction-set simulations of processors often being too
slow, host-compiled or source-level software execution approaches have recently become …

A high-level virtual platform for early MPSoC software development

J Ceng, W Sheng, J Castrillon, A Stulova… - Proceedings of the 7th …, 2009 - dl.acm.org
Multiprocessor System-on-Chips (MPSoCs) are nowadays widely used, but the problem of
their software development persists to be one of the biggest challenges for developers …

Abstract system-level models for early performance and power exploration

A Gerstlauer, S Chakravarty… - 17th Asia and South …, 2012 - ieeexplore.ieee.org
With increasing complexity of today's embedded systems, research has focused on
developing fast, yet accurate high-level and executable models of complete platforms …

Host-compiled simulation of multi-core platforms

A Gerstlauer - Proceedings of 2010 21st IEEE International …, 2010 - ieeexplore.ieee.org
Virtual platform models are a popular approach for virtual prototyping of multi-
processor/multi-core systems-on-chip (MPCSoCs). Such models aid in system-level design …

Scenarios for the identification of objects in legacy systems

T Wiggerts, H Bosma, E Fielt - Proceedings of the Fourth …, 1997 - ieeexplore.ieee.org
We propose an incremental approach to the identification of (business) objects in legacy
applications. In this approach different object identification scenarios can be applied …

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

R Plyaskin, A Masrur, M Geier… - 2010 18th IEEE/IFIP …, 2010 - ieeexplore.ieee.org
Due to the growing complexity of multiprocessor systems-on-chip (MPSoCs), there is an
increasing demand on efficient design space exploration techniques. In addition to the …

TLM+ modeling of embedded HW/SW systems

W Ecker, V Esen, R Schwencker… - … , Automation & Test …, 2010 - ieeexplore.ieee.org
Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-
facto standard in today's SoC design, enabling early SW development. However, due to the …

Host-compiled multicore system simulation for early real-time performance evaluation

P Razaghi, A Gerstlauer - ACM Transactions on Embedded Computing …, 2014 - dl.acm.org
With increasing complexity and software content, modern embedded platforms employ a
heterogeneous mix of multicore processors along with hardware accelerators in order to …

Automatic timing granularity adjustment for host-compiled software simulation

P Razaghi, A Gerstlauer - 17th Asia and South Pacific Design …, 2012 - ieeexplore.ieee.org
Host-compiled simulation has been widely adopted as a practical approach for fast and high-
level evaluation of complex software-intensive systems at early stages of the design …

Heroes: Virtual platform driven integration of heterogeneous software components for multi-core real-time architectures

M Becker, U Kiffmeier, W Mueller - 16th IEEE International …, 2013 - ieeexplore.ieee.org
This article presents the HeroeS virtual platform driven methodology for embedded multi-
core and real-time SW design. The methodology's focus is on early integration, testing and …