Recent progress in physics-based modeling of electromigration in integrated circuit interconnects

WS Zhao, R Zhang, DW Wang - Micromachines, 2022 - mdpi.com
The advance of semiconductor technology not only enables integrated circuits with higher
density and better performance but also increases their vulnerability to various aging …

GridNet: Fast data-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks

H Zhou, W Jin, SXD Tan - … of the 39th International Conference on …, 2020 - dl.acm.org
Electromigration (EM) is a major failure effect for on-chip power grid networks of deep
submicron VLSI circuits. EM degradation of metal grid lines can lead to excessive voltage …

Gridnetopt: Fast full-chip em-aware power grid optimization accelerated by deep neural networks

H Zhou, Y Liu, W Jin, SXD Tan - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article presents a fast full-chip electromigration (EM) aware IR drop constrained
optimization framework, named GridNetOpt, for on-chip power grid networks accelerated by …

Interconnect electromigration modeling and analysis for nanometer ICs: From physics to full-chip

S Tan, Z Sun, S Sadiqbatcha - IPSJ Transactions on System and LSI …, 2020 - jstage.jst.go.jp
In this article, we will present recent advances in VLSI reliability effects with a focus on
electromigration (EM) failure/aging effect on interconnects, which is one of the most …

Reliable power grid network design framework considering EM immortalities for multi-segment wires

H Zhou, S Yu, Z Sun, SXD Tan - 2020 25th Asia and South …, 2020 - ieeexplore.ieee.org
This paper presents a new power grid network design and optimization technique that
considers the new EM immortality constraint due to EM void saturation volume for multi …

An Electromigration-Aware Wire Sizing Methodology via Particle Swarm Optimization

O Axelou, K Kolomvatsos, G Floros… - Proceedings of the …, 2024 - dl.acm.org
As semiconductor manufacturing technologies progress beyond the current 3nm, the
demand for more compact and powerful VLSI circuits obliges on-chip power grid networks to …

Robust power grid network design considering EM aging effects for multi-segment wires

H Zhou, L Chen, SXD Tan - Integration, 2021 - Elsevier
This paper presents a number of power grid network design and optimization techniques
that consider the electromigration (EM) effects for multi-segment interconnect wires. First, we …

GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder

Y Liu, SXD Tan - 2024 25th International Symposium on …, 2024 - ieeexplore.ieee.org
Electromigration (EM) remains the primary failure mechanism for copper-based
interconnects in today's and future nanometer chip technologies. To ensure the longevity of …

Electromigration and IR Voltage Drop Reduction Technique on DDR Memory Block Using Power Grid Augmentation

A Marni, KS Pande - 2021 5th International Conference on …, 2021 - ieeexplore.ieee.org
As technology scales down to nanometres it severely affects the IR (Voltage) drop. Although
checking this problem in the earlier stages can speed up the analysis, not many tools are …

[PDF][PDF] EM lifetime constrained optimization for multi-segment power grid networks

H Zhou, Z Sun, S Sadiqbatcha… - Dependable Embedded …, 2021 - library.oapen.org
On-chip power supply or power-ground (P/G) networks provide power to the circuit modules
in a chip from external power supplies. Since power grid wires experience the largest …