A modified pulse swallow frequency divider for fractional-N PLL
P Yan, J Jiang, J Liu, Y Tang - IEICE Electronics Express, 2020 - jstage.jst.go.jp
A modified pulse swallow frequency divider for fractional-N frequency synthesizers was
designed and implemented in a 0.18 µm CMOS process. The proposed structure inserts a …
designed and implemented in a 0.18 µm CMOS process. The proposed structure inserts a …
[PDF][PDF] A Hybrid Topology for Frequency Divider using PLL Application
A Pon, R Parameshwaran - Indian Journal of Science and …, 2016 - researchgate.net
In this paper, we present a new type of odd integer divider topology which consume low
power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 …
power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 …