The deposition of films with nonuniform residual stress can induce local changes in wafer
shape and contribute to overlay errors with magnitudes that may be significant in advanced …

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid
growth. Technological advances in IC materials and design have produced generations of …

A method for analyzing overlay errors in lithography is described. Interfield sampling and
intrafield sampling are first conducted to sample multiple positions on each of the wafers …

In one embodiment, a semiconductor target for determin ing overlay error, if any, between
two or more Successive layers of a Substrate or between two or more separately gen erated …

BACKGROUND The performance of integrated circuits typically exhibits statistical
fluctuations due to process variations during the manufacturing processes. Devices and …

The present invention relates generally to semiconductor processing tools, and more
particularly, to a feature dimen sion deviation correction system, method and program prod …

Abstract Systems, methods and computer program products generally include a vector by
vector subtraction method per wafer. A first layer is exposed to form a pattern image on a …

Methods and processes for establishing a rework threshold for layers applied after thermal
processing during fabrication of semiconductor devices are provided. One method includes …

BACKGROUND Silicon wafers are currently manufactured in a sequence of steps, where
each step places a pattern of material on the wafer. By building up Successive layers of …

In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay
a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein …