Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems
The last level on-chip cache (LLC) is becoming bigger and more complex to effectively
support the various localities coming from multiple cores and threads running concurrently in …
support the various localities coming from multiple cores and threads running concurrently in …
Static energy reduction by performance linked dynamic cache resizing
S Chakraborty, HK Kapoor - 2016 IFIP/IEEE International …, 2016 - ieeexplore.ieee.org
The increased power density with short channel effect in modern transistors significantly
increases the leakage energy consumptions of on-chip Last Level Caches (LLCs) in recent …
increases the leakage energy consumptions of on-chip Last Level Caches (LLCs) in recent …
Towards a better cache utilization by selective data storage for CMP last level caches
Tiled based CMP (TCMP) has become the essential next generation scalable multicore
architecture. The cores in TCMP commonly share a large sized Last Level Cache. NUCA is …
architecture. The cores in TCMP commonly share a large sized Last Level Cache. NUCA is …
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs
S Chakraborty, HK Kapoor - Microprocessors and Microsystems, 2017 - Elsevier
Advancement in semiconductor technology increases power density in recent Chip Multi-
Processors (CMPs) which significantly increases the leakage energy consumptions of on …
Processors (CMPs) which significantly increases the leakage energy consumptions of on …
The diego lab graph based gene normalization system
R Sullivan, R Leaman… - 2011 10th International …, 2011 - ieeexplore.ieee.org
Gene entity normalization, the mapping of a gene mention in free text to a unique identifier,
is one of the primary subtasks in the biomedical information extraction pipeline. Gene entity …
is one of the primary subtasks in the biomedical information extraction pipeline. Gene entity …
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs
Rapid growth in semiconductor technology permits to integrate multiple number of processor
cores with multi-level on-chip caches. Integration of more on-chip components increases the …
cores with multi-level on-chip caches. Integration of more on-chip components increases the …
Performance constrained static energy reduction using way-sharing target-banks
S Chakraborty, S Das… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
Most of chip-multiprocessors share a common large sized last level cache (LLC). In non-
uniform cache access based architectures, the LLC is divided into multiple banks to be …
uniform cache access based architectures, the LLC is divided into multiple banks to be …
Utility aware snoozy caches for energy efficient chip multi-processors
Heavy leakage power consumption of on-chip last level caches (LLCs) has become the
primary obstacle for architecting chip multi-processors (CMPs) in recent times. As leakage …
primary obstacle for architecting chip multi-processors (CMPs) in recent times. As leakage …
Cache Memory Architectures for Handling Big Data Applications: A Survey
P Das - Smart Computing Paradigms: New Progresses and …, 2020 - Springer
Cache memory plays an important role in the efficient execution of today's big data-based
applications. The high-performance computer has multicore processors to support parallel …
applications. The high-performance computer has multicore processors to support parallel …
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors
Advancement in semiconductor technology has packed more and more transistors on the
chip leading to more processing power. This processing power comes at the cost of heavy …
chip leading to more processing power. This processing power comes at the cost of heavy …