Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
Multichannel, low nonlinearity time-to-digital converters based on 20 and 28 nm FPGAs
H Chen, DDU Li - IEEE Transactions on Industrial Electronics, 2018 - ieeexplore.ieee.org
This paper presents low nonlinearity, compact, and multichannel time-to-digital converters
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
4.5 a 9.25 GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology
The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the
communication industry to set extremely challenging requirements on the integrated jitter of …
communication industry to set extremely challenging requirements on the integrated jitter of …
Linear CMOS -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop
A linear CMOS voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-
GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process …
GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process …
24.7 A 673µW 1.8-to-2.5 GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT …
The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF
transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a …
transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a …
A 0.5-V 1.6-mW 2.4-GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28-nm CMOS
N Pourmousavian, FW Kuo… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL)
powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs …
powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs …
Low-power MEMS-based pierce oscillator using a 61-MHz capacitive-gap disk resonator
A 61-MHz Pierce oscillator constructed in 0.35-μm CMOS technology and referenced to a
polysilicon surface-micromachined capacitive-gap-transduced wineglass disk resonator has …
polysilicon surface-micromachined capacitive-gap-transduced wineglass disk resonator has …
A 529-μW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
A watt-level phase-interleaved multi-subharmonic switching digital power amplifier
A Zhang, MSW Chen - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA)
architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output …
architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output …
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
This article presents a fractional-digital multiplying delay-locked loop (MDLL) that uses a
digital-to-time converter (DTC) for controlling the reference injection timing to support the …
digital-to-time converter (DTC) for controlling the reference injection timing to support the …