[HTML][HTML] High-k/Ge MOSFETs for future nanoelectronics

Y Kamata - Materials today, 2008 - Elsevier
Recently developed high-permittivity (k) materials have reopened the door to Ge as a
channel material in metal-oxide-semiconductor field-effect transistors (MOSFETs). High-k/Ge …

Transistor with threshold voltage set notch and method of fabrication thereof

R Arghavani, P Ranade, L Shifren… - US Patent …, 2014 - Google Patents
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Low power semiconductor transistor structure and method of fabrication thereof

L Shifren, P Ranade, SE Thompson… - US Patent …, 2013 - Google Patents
Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …

Advanced transistors with punch through suppression

L Shifren, P Ranade, PE Gregory… - US Patent …, 2013 - Google Patents
An advanced transistor with punch through suppression includes a gate with length Lg, a
well doped to have a? rst concentration of a dopant, and a screening region positioned …

[图书][B] Extended defects in germanium: Fundamental and technological aspects

C Claeys, E Simoen - 2009 - Springer
The first observations of plastically deformed germanium made immediately clear that
dislocations introduced during a high-temperature deformation create acceptor states [1–5] …

Process for manufacturing an improved analog transistor

L Shifren, SE Thompson, PE Gregory - US Patent 8,748,270, 2014 - Google Patents
3,958.266 A 5, 1976 Athanas 4,000,504 A 12/1976 Berger 4,021,835 A 5, 1977 Etoh et al.
4,242,691 A 12/1980 Kotani et al. 4,276.095 A 6/1981 Beilstein, Jr. et al. 4,315,781 A 2f1982 …

Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of …

D Zhao, P Ranade, B McWilliams - US Patent 9,093,550, 2015 - Google Patents
(51) Int. Cl(57) ABSTRACT tion 21/8238 (2006.01) Semiconductor manufacturing processes
include forming HOIL 21/82(2006.015 conventional channel field effect transistors (FETs) …

Method for reducing punch-through in a transistor device

L Shifren, T Ema - US Patent 8,377,783, 2013 - Google Patents
Punch-through in a transistor device is reduced by forming a well layer in an implant region,
forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped …

Effect of rapid thermal annealing on crystallization and stress relaxation of SiGe nanoparticles deposited by ICP PECVD

F Ravaux, NS Rajput, J Abed, L George, M Tiner… - RSC …, 2017 - pubs.rsc.org
This work demonstrates the viability of direct fabrication utilizing a single (deposition/anneal)
process for polycrystalline silicon germanium sub-micro particles. The process combines …

Semiconductor devices having fin structures and fabrication methods thereof

T Hoffmann, SE Thompson - US Patent 9,054,219, 2015 - Google Patents
A method of fabricating semiconductor devices includes pro viding a semiconducting
Substrate. The method also includes defining a heavily doped region at a surface of the …