Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …
L Shifren, P Ranade, PE Gregory… - US Patent …, 2013 - Google Patents
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a? rst concentration of a dopant, and a screening region positioned …
The first observations of plastically deformed germanium made immediately clear that dislocations introduced during a high-temperature deformation create acceptor states [1–5] …
3,958.266 A 5, 1976 Athanas 4,000,504 A 12/1976 Berger 4,021,835 A 5, 1977 Etoh et al. 4,242,691 A 12/1980 Kotani et al. 4,276.095 A 6/1981 Beilstein, Jr. et al. 4,315,781 A 2f1982 …
L Shifren, T Ema - US Patent 8,377,783, 2013 - Google Patents
Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped …
This work demonstrates the viability of direct fabrication utilizing a single (deposition/anneal) process for polycrystalline silicon germanium sub-micro particles. The process combines …
T Hoffmann, SE Thompson - US Patent 9,054,219, 2015 - Google Patents
A method of fabricating semiconductor devices includes pro viding a semiconducting Substrate. The method also includes defining a heavily doped region at a surface of the …