RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey

Y Nasser, J Lorandel, JC Prévotet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …

Variability aware modeling of SoCs: From device variations to manufactured system yield

M Miranda, B Dierickx, P Zuber… - … on Quality Electronic …, 2009 - ieeexplore.ieee.org
As CMOS technology feature sizes decrease, random within-die and inter-die process
variations more and more jeopardize SoC parametric and functional yield. Largely …

Generating a useful theory of software engineering

S Adolph, P Kruchten - 2013 2nd SEMAT Workshop on a …, 2013 - ieeexplore.ieee.org
We argue a theory of software engineering must be useful to practitioners and explain the
phenomena they are experiencing. Useful theories of software engineering can be …

Power analysis

K Tu, X Tang, C Yu, L Josipović, Z Chu - FPGA EDA: Design Principles …, 2024 - Springer
Power dissipation has become one of the top concern in the development of new integrated
circuits. In this chapter, power analysis techniques for FPGA are introduced. The power …

Process-driven variability analysis of single and multiple voltage–frequency island latency-constrained systems

D Marculescu, S Garg - … Aided Design of Integrated Circuits and …, 2008 - ieeexplore.ieee.org
The problem of determining bounds for application completion times running on generic
systems comprising single or multiple voltage-frequency islands (VFIs) with arbitrary …

Simulation based power estimation for digital CMOS technologies

J Alexander - 2008 - etd.auburn.edu
The estimation of power in digital CMOS circuits has become a significant problem,
especially for present day semiconductor technologies. Finding a balance between …

A MODEL FOR EARLY POWER ESTIMATION ON MULTIRATE DIGITAL SYSTEMS

G Battisti - 2022 - tesidottorato.depositolegale.it
Le crescenti esigenze di capacità di connessione per le aree rurali, remote e anche urbane
probabilmente aumenteranno il costo della pura copertura terrestre. In questo scenario le …

An Efficient Computer-Aided Design Methodology for FPGA&ASIC High-Level Power Estimation Based on Machine Learning

Y Nasser - 2019 - theses.hal.science
Nowadays, advanced digital systems are required to address complex functionnalities in a
very wide range of applications. Systems complexity imposes designers to respect different …

Reduction of Crosstalk Pessimism with Consideration of Logic and Timing Correlations

M Palla - 2009 - media.suub.uni-bremen.de
Accurate estimation of crosstalk has become a key issue in Static Timing Analysis of modern
deep-submicron (DSM) digital circuits. The inherent logic and timing properties of the circuit …