Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs
G Garegnani, V Fiori, G Gouget, F Monsieur… - Microelectronics …, 2016 - Elsevier
We present an experimental technique and a Finite Element thermal simulation for the
determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self …
determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self …
Using TSVs for thermal mitigation in 3D circuits: Wish and truth
3D technology is envisioned to offer advanced integration capabilities, enabling
heterogeneous system integration and offering improved performance and reduced power …
heterogeneous system integration and offering improved performance and reduced power …
Thermal effects of silicon thickness in 3-D ICs: Measurements and simulations
This paper presents the impact of silicon thickness on the temperature and the thermal
resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks …
resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks …
Effective thermal modeling of a thin film snubber resistor for power modules
R Watanabe, K Izawa, S Kajiya… - Nonlinear Theory and …, 2020 - jstage.jst.go.jp
This paper proposes an effective thermal compact modeling method for a thin film resistor
that is dedicated for snubber circuits in power electronic modules. The objective compact …
that is dedicated for snubber circuits in power electronic modules. The objective compact …
Numerical analysis of thermal effects in SOI MOSFET Flip-Chip packages: Multi-scale studies on isolated transistors and global simulations
G Garegnani, V Fiori… - 2016 6th Electronic …, 2016 - ieeexplore.ieee.org
We present numerical simulations of thermal phenomena in SOI MOSFETs flip-chip
packages. We consider the effects of package environment on isolated transistors …
packages. We consider the effects of package environment on isolated transistors …