Nanotechnology-based fabrication is expected to offer the extra density and potential
performance to take electronic circuits beyond the scaling limits reached by CMOS …

In recent years, research in the space community has shown a growing interest in Artificial
Intelligence (AI), mostly driven by systems miniaturization and commercial competition. In …

The very high integration levels reached by VLSI technologies for SRAM-based field
programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced …

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is
an increasingly important subject as FPGAs are used in radiation environments such as …

Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …

The use of approximate logic circuits in error mitigation techniques has appeared in the
recent years as a way of achieving a sufficient fault coverage at a reduced cost, substituting …

For digital system designs, triple modular redundancy (TMR), which is a 3-tuple version of N-
modular redundancy is widely preferred for many mission-control and safety-critical …

This paper presents a novel design flow for the implementation of digital systems onto
SRAM-based FPGAs with soft error mitigation properties. Traditional fault …

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive
in terms of FPGA resource utilization and power consumption. For certain applications …

Soft error has increasingly become a critical concern for SRAM-based field programmable
gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration …