A reconfigurable LDPC decoder optimized for 802.11 n/ac applications

I Tsatsaragkos, V Paliouras - IEEE Transactions on Very Large …, 2017 - ieeexplore.ieee.org
This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable for
the 802.11 n/ac (WiFi) standard. The innovative features of the proposed decoder relate to …

Review on 5G NR LDPC code: recommendations for DTTB system

F Li, C Zhang, K Peng, AE Krylov, AA Katyushnyj… - IEEE …, 2021 - ieeexplore.ieee.org
The freeze of the 5th generation new radio (5G NR) Release 16 indicates that 5G
development has stepped into a new stage. The application of a dedicated low-density …

Flexible LDPC decoder architectures

M Awais, C Condo - VLSI Design, 2012 - Wiley Online Library
Flexible channel decoding is getting significance with the increase in number of wireless
standards and modes within a standard. A flexible channel decoder is a solution providing …

A high-efficiency segmented reconfigurable cyclic shifter for 5G QC-LDPC decoder

HM Lam, S Lu, H Qiu, M Zhang, H Jiao… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for
5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one …

A flexible and high parallel permutation network for 5G LDPC decoders

Z Zhong, Y Huang, Z Zhang, X You… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Cyclic shifting is usually applied in quasi-cyclic low-density parity-check (QC-LDPC)
decoders for permutation operations. In this brief, we propose a flexible and high parallel …

A universal efficient circular-shift network for reconfigurable quasi-cyclic LDPC decoders

S Song, H Cui, Z Wang - … on Very Large Scale Integration (VLSI …, 2022 - ieeexplore.ieee.org
Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication
standards usually have multiple code rates and block lengths. Therefore, reconfigurable …

A high-throughput multi-mode LDPC decoder for 5G NR

S Pourjabar, GS Choi - arXiv preprint arXiv:2102.13228, 2021 - arxiv.org
This paper presents a partially parallel low-density parity-check (LDPC) decoder designed
for the 5G New Radio (NR) standard. The design is using a multi-block parallel architecture …

A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio

S Pourjabar, GS Choi - International Journal of Circuit Theory …, 2022 - Wiley Online Library
This paper presents a partially parallel low‐density parity‐check (LDPC) decoder for the 5G
New Radio (NR) standard. The design is using a multiblock parallel architecture with a …

Ultra low power QC-LDPC decoder with high parallelism

Y Cui, X Peng, Z Chen, X Zhao, Y Lu… - 2011 IEEE …, 2011 - ieeexplore.ieee.org
This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-
density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo …

[HTML][HTML] FEC design for remote control and data transmission of aeronautic and astronautic vehicles

Q Huang, M Zhang, W Zulin, X Zhang - Chinese Journal of Aeronautics, 2019 - Elsevier
This paper focuses on the advanced Forward Error Correction (FEC) based on Low-Density
Parity-Check (LDPC) codes for remote control and data transmission of Aeronautic and …