[图书][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

Boolean satisfiability in electronic design automation

JP Marques-Silva, KA Sakallah - Proceedings of the 37th Annual Design …, 2000 - dl.acm.org
Boolean Satisfiability (SAT) is often used as the underlying model for a significant and
increasing number of applications in Electronic Design Automation (EDA) as well as in many …

[PDF][PDF] Algorithms for solving boolean satisfiability in combinational circuits

L Guerra e Silva, LM Silveira… - Proceedings of the …, 1999 - dl.acm.org
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds
application in test pattern generation, delay-fault testing, combinational equivalence …

Logic synthesis in a nutshell

JHR Jiang, S Devadas - Electronic Design Automation, 2009 - Elsevier
Publisher Summary Logic synthesis is the process of automatic production of logic
components, in particular digital circuits. It is a subject about how to abstract and represent …

Securing module-less synthesis on cyberphysical digital microfluidic biochips from malicious intrusions

S Chakraborty, C Das… - 2018 31st International …, 2018 - ieeexplore.ieee.org
Digital Microfluidic biochips (DMFB's) lack the ability to recover from the errors incurred at
assay runtime, which leads to erroneous assay results. Cyberphysical DMFB (CP-DMFB) …

Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations

FN Esirci, AA Bayrakci - Design, Automation & Test in Europe …, 2017 - ieeexplore.ieee.org
Hardware Trojan (HT) detection methods based on the side channel analysis deeply suffer
from the process variations. In order to suppress the effect of the variations, we devise a …

Realistic delay modeling in satisfiability-based timing analysis

LG e Silva, JPM Silva, LM Silveira… - … '98. Proceedings of the …, 1998 - ieeexplore.ieee.org
Circuit delay computation taking into account the existence of false paths represents a
significant and computationally complex problem. Existing research work has focused …

Maximum circuit activity estimation using pseudo-boolean satisfiability

H Mangassarian, A Veneris… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
With lower supply voltages, increased integration densities and higher operating
frequencies, power grid verification has become a crucial step in the very large-scale …

Functional timing analysis made fast and general

YT Chung, JHR Jiang - Proceedings of the 49th Annual Design …, 2012 - dl.acm.org
Functional, in contrast to structural, timing analysis is accurate, but computationally
expensive in refuting false critical paths. Although satisfiability-based analysis using timed …

CCP: Common case promotion for improved timing error resilience with energy efficiency

L Wan, D Chen - Proceedings of the 2012 ACM/IEEE international …, 2012 - dl.acm.org
Better-Than-Worst-case (BTW) design has been proposed as an alternative way to operate
a circuit by deliberately allowing timing errors for rare cases and rectifying them with error …