Power dissipated during test is a constraint when it comes to test time reduction. In this work,
we show that for a given test the minimum test application time is achieved when the total …

A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed
synchronous clock period. Typical test cycles may produce high signal activity and to keep …

During wafer sort, the fabricated chips are subjected to tests that verify if they meet the
design specification. Test application time plays a critical role while verifying large volume of …

With scale down in technology, size and complexity of integrated circuits increase. The scan
method is the most popular technique of testing sequential circuits today. In this method, ip …

Conventionally, testing uses clock with fixed period during scan shift, which make the tests
long. In this work, we propose two methods, scaling supply voltage and scaling frequency …