Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications
R Chau, S Datta, A Majumdar - … Integrated Circuit Symposium …, 2005 - ieeexplore.ieee.org
This paper highlights the opportunities and challenges of III-V nanoelectronics for future high-
speed, low-power digital logic applications. III-V materials in general have significantly …
speed, low-power digital logic applications. III-V materials in general have significantly …
Novel ferroelectric FET based synapse for neuromorphic systems
A compact nanoscale device emulating the functionality of biological synapses is an
essential element for neuromorphic systems. Here we present for the first time a synapse …
essential element for neuromorphic systems. Here we present for the first time a synapse …
Physical thickness 1. x nm ferroelectric HfZrOx negative capacitance FETs
Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally
demonstrated with physical thickness 1.5 nm, SS= 52 mV/dec, hysteresis free (threshold …
demonstrated with physical thickness 1.5 nm, SS= 52 mV/dec, hysteresis free (threshold …
Ferroelectric HfZrOx Ge and GeSn PMOSFETs with Sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved Ids
We report the first ferroelectric (FE) HfZrO x (HZO) Ge and GeSn pMOSFETs with sub-60
mV/decade subthreshold swing (SS)(40~ 43 mV/decade), negligible hysteresis, and …
mV/decade subthreshold swing (SS)(40~ 43 mV/decade), negligible hysteresis, and …
The evolution of scaling from the homogeneous era to the heterogeneous era
M Bohr - 2011 international electron devices meeting, 2011 - ieeexplore.ieee.org
Traditional MOSFET scaling served our industry well for more than three decades by
providing continuous improvements in transistor performance, power and cost. This was the …
providing continuous improvements in transistor performance, power and cost. This was the …
Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages
A novel transistor design which utilizes positive feedback to achieve steep switching
behavior is proposed and demonstrated. The feedback (FB) FET exhibits very low …
behavior is proposed and demonstrated. The feedback (FB) FET exhibits very low …
Process and packaging innovations for Moore's law continuation and beyond
R Chau - 2019 IEEE International Electron Devices Meeting …, 2019 - ieeexplore.ieee.org
This presentation describes various revolutionary process and packaging technologies on
the horizon that will (i) extend Moore's Law scaling through and beyond the next decade and …
the horizon that will (i) extend Moore's Law scaling through and beyond the next decade and …
A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics
H Kam, DT Lee, RT Howe… - … Devices Meeting, 2005 …, 2005 - ieeexplore.ieee.org
An accumulation-mode design for nanometer-scale electromechanical-gate field effect
transistors (NEMFETs) is proposed and studied via simulation. In the off state, the gate …
transistors (NEMFETs) is proposed and studied via simulation. In the off state, the gate …
High-Performance Vertical β-Ga2 O3 Schottky Barrier Diodes Featuring P-NiO JTE with Adjustable Conductivity
We demonstrate a novel conductivity-controlled junction termination extension (JTE)
technique using p-type NiO–a key element for potential commercialization of Ga 2 O 3 …
technique using p-type NiO–a key element for potential commercialization of Ga 2 O 3 …
[图书][B] Low-power electronics design
C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …
affecting the design of high-performance chips and portable devices. The study of power …