Cloud computing provisions scalable resources for high performance industrial applications.
Cloud providers usually offer two types of usage plans: reserved and on-demand. Reserved …

In modern VLSI design, more than 30% of power consumption is caused by clock networks
due to their large capacitance demand and high switching frequency. Prior research on …

One of the challenging stages in Very Large Scale Integration (VLSI) design is clock network
synthesis that plays an important role in the circuit performance. Digital Integrated Circuits …

Clock buffer and wire sizing are intertwined problems that also greatly impact power
consumption and skew in clock trees. Due to their complexity, they are often solved …

Comparing with super-threshold designs, clock tree design in near-threshold voltage (NTV)
region is more susceptive to signal slew, and timing violations occur much more often due to …

This chapter collects recent advances in using convex optimization techniques to perform
sizing of digital circuits. Convex optimization techniques provide an undeniably attractive …

Cloud computing offers a pool of various cloud resources, including scalable computing
instances, database instances, storage, network bandwidth, etc. which are delivered to …

Gate sizing and clock buffer and wire sizing are intertwined problems that greatly impact the
trade-off between the power consumption and timing metrics of digital integrated circuits …

Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The
performance of the IC highly depends on the clock network synthesis which makes this …