A programmable logic device is programmed to perform arithmetic operations in an internal
format that, unlike known standard formats that store numbers in normalized form and …

A specialized processing block for a programmable logic device includes circuitry for
performing multiplications and sums thereof, as well as circuitry for rounding the result. The …

(57) ABSTRACT A specialized processing block for a programmable logic device
incorporates a fundamental processing unit that per forms a sum of two multiplications …

4.215. 406 A 7, 1980 Gomola et al. before adding. In one embodiment, this allows all but the
final 42 15.407 A 7, 1980 Gomola et al. addition to take place in specialized processing …

A specialized processing block in a programmable integrated circuit device is configurable
to perform floating-point arithmetic operations at selectable different precisions. The …

A plurality of specialized processing blocks in a programmable logic device, including
multipliers and circuitry for adding results of those multipliers, can be configured as a larger …

(56) References Cited 5,636,150 A 6/1997 Okamoto 5,636,368 A 6/1997 Harrison et al. US
PATENT DOCUMENTS 5,640,578 A 6/1997 Balmer et al. 5,644,519 A 7, 1997 Yatim et al …

A programmable logic device can be configured as a finite impulse response (FIR) filter
capable of operating in either interpolation mode or decimation mode and of switching …

Multiplier-accumulator circuitry includes circuitry for form ing a plurality of partial products of
multiplier and multipli candinputs, carry-save adder circuitry for adding together the partial …

Abstract Digital signal processing (“DSP”) circuit blocks are provided that can more easily
work together to perform larger (eg, more complex and/or more arithmetically precise) DSP …