Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration

JJ Davis, PYK Cheung - 2014 24th International Conference on …, 2014 - ieeexplore.ieee.org
While allowing for the fabrication of increasingly complex and efficient circuitry, transistor
shrinkage and count-per-device expansion have major downsides: chiefly increased …

Hardware Implementation of High Speed Fault-Tolerant Parallel Accelerator

W Ma - 2024 IEEE 17th International Conference on Solid …, 2024 - ieeexplore.ieee.org
Process advancements and single-event effects in terrestrial environments have heightened
the importance of fault-tolerant design for FPGA-based digital circuits. This paper presents a …

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators

JJ Davis, PYK Cheung - International Symposium on Applied …, 2016 - Springer
As the threat of fault susceptibility caused by mechanisms including variation and
degradation increases, engineers must give growing consideration to error detection and …

Reducing overheads for fault-tolerant datapaths with dynamic partial reconfiguration

JJ Davis, PYK Cheung - 2014 IEEE 22nd Annual International …, 2014 - ieeexplore.ieee.org
As process scaling and transistor count inflation continue, silicon chips are becoming
increasingly susceptible to faults. Although FPGAs are particularly vulnerable to these …

[PDF][PDF] Low-overhead fault-tolerant logic for field-programmable gate arrays

J Davis - 2015 - core.ac.uk
While allowing for the fabrication of increasingly complex and efficient circuitry, transistor
shrinkage and count-per-device expansion have major downsides: chiefly increased …