Real-time fault-tolerance with hot-standby topology for conditional sum adder

A Mukherjee, AS Dhar - Microelectronics Reliability, 2015 - Elsevier
This paper presents the design philosophy of a fault tolerant conditional sum adder that uses
hot-standby technique, which is an online swapping process of faulty components of a circuit …

Design of fault tolerant adders: a review

GH Bin Talib, AH El-Maleh, SM Sait - Arabian Journal for Science and …, 2018 - Springer
Arithmetic circuits, especially the adder, are the heart of any computing system that
comprises numerous processing units ranging from small digital systems to supercomputers …

Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture

A Mukherjee, AS Dhar - 2012 International Symposium on …, 2012 - ieeexplore.ieee.org
Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By
incorporating fault tolerant features in any architecture, reliability and durability of the system …

Double-fault tolerant architecture design for digital adder

A Mukherjee, AS Dhar - Proceedings of the 2014 IEEE Students …, 2014 - ieeexplore.ieee.org
In the era of deep sub-micron technology, probability of chip failure has been increased with
increase in chip density. A system must be fault tolerant to decrease the failure rate and …

Design of Multi-bit Fault Tolerant Array Multiplier

VK Verma, A Mukherjee - 2024 IEEE International Conference …, 2024 - ieeexplore.ieee.org
A multiplier is a major component in digital signal processors (DSP) for performing fast
Fourier transform (FFT) and filtering. In this paper, a multi-bit fault tolerant array multiplier …

Design of a Self-reconfigurable Incrementer for Fault Tolerant VLSI Architecture

K Sahu, A Mukherjee - 2023 IEEE Silchar Subsection …, 2023 - ieeexplore.ieee.org
Fault tolerance is the ability of a system to detect and recover from a fault and to continue
operating normally even with a broken component. It can increase the system's …

[PDF][PDF] Triple-fault tolerant architecture design for ripple carry adder

S Mabjani, K Subramanyam - International Journal, 2015 - ijeert.ijrsset.org
ABSTRACT A system must be fault tolerant to decrease the failure rate and increase the
reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off …

[PDF][PDF] ساختار جدید از یک مقایسه گر تحمل پذیر خطا

علوی, امین, سید مهدوی چابک - نشریه مهندسی برق و الکترونیک ایران, 2019‎ - jiaeee.com
خطا ری گر تحمل پذ سه ی مقا ک یاز دی ساختار جد Page 1 يسدنهم نمجنا هلجم ناريا کينورتکلا و قرب
- اس مهدزناش ل مود هرامش ناتسبات 1398 Journal of Iranian A ssociation of E lectrical and E …

[PDF][PDF] Implementation of Double Fault Tolerant Architecture Design for Digital Adder

L Battula, P Satishchandra, P Santosh - ijrsset.org
A system must be fault tolerant to decrease the failure rate and increase the reliability of it.
Multiple faults can affect a system simultaneously and there is a trade-off between area …