Design for manufacturability and reliability in extreme-scaling VLSI

B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan - Science China Information …, 2016 - Springer
In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

[HTML][HTML] A review of the study on the electromigration and power electronics

MK Rahman, AMM Musa, B Neher, KA Patwary… - Journal of Electronics …, 2016 - scirp.org
Electromigration is a main challenge in the pursuit of power electronics, because physical
limit to increase current density in power electronics is electromigration (EM), whereas much …

TSV-based 3-D ICs: Design methods and tools

T Lu, C Serafy, Z Yang, SK Samal… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …

Electromigration-aware analog Router with multilayer multiport terminal structures

R Martins, N Lourenco, A Canelas, N Horta - Integration, 2014 - Elsevier
The combined effects of current densities and temperature in the interconnects may cause
the failure of a circuit due to electromigration (EM). EM becomes increasingly more relevant …

Recovery-aware proactive TSV repair for electromigration lifetime enhancement in 3-D ICs

S Wang, T Kim, Z Sun, SXD Tan… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Electromigration (EM) becomes a major reliability concern in 3-D integrated circuits (3-D
ICs). To mitigate this problem, a typical solution is to use through-silicon via (TSV) …

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs

DK Maity, SK Roy, C Giri - Integration, 2024 - Elsevier
Abstract The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated
Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it …

MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5 D/3D IC

T Zhu, Q Wang, Y Lin, R Wang, R Huang - arXiv preprint arXiv:2411.12690, 2024 - arxiv.org
Thermomechanical stress induced by through-silicon vias (TSVs) plays an important role in
the performance and reliability analysis of 2.5 D/3D ICs. While the finite element method …

Electromigration-aware local-via allocation in power/ground TSVs of 3-D ICs

S Wang, MB Tahoori - IEEE Transactions on Very Large Scale …, 2017 - ieeexplore.ieee.org
With increasing temperature and current density, electromigration (EM) becomes a major
interconnect reliability concern for 3-D integrated-circuits (3-D ICs). In 3-D power delivery …

Electromigration-aware clock tree synthesis for TSV-based 3D-ICs

T Lu, A Srivastava - Proceedings of the 25th edition on Great Lakes …, 2015 - dl.acm.org
In 3D-IC technology, electromigration (EM) degradation has become severe due to the high
thermal-mechanical stress induced by the Through-Silicon-Vias (TSVs). However, little has …

Recovery-aware proactive TSV repair for electromigration in 3D ICs

S Wang, H Zhao, SXD Tan… - Design, Automation & …, 2017 - ieeexplore.ieee.org
Electromigration (EM) becomes a major reliability concern in three-dimensional integrated-
circuits (3D ICs). To mitigate this problem, a typical solution is to use TSV redundancy in a …