Trending IC design directions in 2022

CH Chan, L Cheng, W Deng, P Feng… - Journal of …, 2022 - iopscience.iop.org
For the non-stop demands for a better and smarter society, the number of electronic devices
keeps increasing exponentially; and the computation power, communication data rate, smart …

Low-power SAR ADCs: Basic techniques and trends

P Harpe - IEEE Open Journal of the Solid-State Circuits Society, 2022 - ieeexplore.ieee.org
With the advent of small, battery-powered devices, power efficiency has become of
paramount importance. For analog-to-digital converters (ADCs), the successive …

A 2.87 μW 1kHz-BW 94.0 dB-SNDR 2-0 MASH ADC using FIA with dynamic-body-biasing assisted CLS technique

Y Hu, Y Zhao, W Qu, L Ye, M Zhao… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
Micro-power ΔΣ modulators are suitable for low-bandwidth, high-precision applications,
such as smart sensors, biomedical signal processing and battery-powered IoT devices. They …

Fully dynamic discrete-time ΔΣ ADC using closed-loop two-stage cascoded floating inverter amplifiers

A Matsuoka, T Nezuka, T Iizuka - IEEE Transactions on Circuits …, 2021 - ieeexplore.ieee.org
This brief proposes a fully dynamic discrete-time ADC using closed-loop two-stage
cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as …

A 65-dB-SNDR pipelined SAR ADC Using PVT-robust capacitively degenerated dynamic amplifier

H Yoon, C Lee, T Kim, Y Kwon… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents a process, voltage, and temperature (PVT)-robust capacitively
degenerated dynamic amplifier as the residue amplifier of the low-power pipelined …

A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2–0 MASH Delta-Sigma ADC

L Meng, Y Hu, Y Zhao, W Qu, L Ye… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital
converter (ADC) for low-power and high-precision applications. It implements the …

Fully dynamic zoom-ADC based on improved swing-enhanced FIAs using CLS technique with 1250× bandwidth/power scalability

Y Zhao, M Zhao, Z Tan - … on Circuits and Systems II: Express …, 2023 - ieeexplore.ieee.org
This brief proposes a fully dynamic zoom ADC based on improved swing-enhanced floating-
inverter amplifiers (SEFIAs) using the correlated-level-shifting (CLS) technique with …

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier

X Tang, X Yang, J Liu, Z Wang, W Shi… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents a bandwidth-adaptive pipelined successive approximation register
(SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The …

A 100-to-10-kHz 5.4-to-216-μW power-efficient readout circuit employing closed-loop dynamic amplifier for MEMS capacitive accelerometer

L Zhong, S Liu, P Shang, W Cao… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
Micro-electromechanical systems (MEMS) capacitive accelerometer for the Internet of
Things (IoT) applications is required to operate at various sampling frequencies while …

An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique

T Xie, TH Wang, Z Liu, S Li - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
To design a low-oversampled high-resolution noise-shaping successive approximation
register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be …