Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A Low-Noise Fractional- Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications
In this paper, we propose a 60-GHz fractional-digital frequency synthesizer aimed at
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
Analysis of a 28-nm CMOS fast-lock bang-bang digital PLL with 220-fs RMS jitter for millimeter-wave communication
This article analyses and demonstrates a 22.5-27.7-GHz fast-lock low-phase-noise bang-
bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A …
bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A …
A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5-GHz bandwidth
This article presents a 16-GHz frequency-modulated continuous-waveform (FMCW)
modulator for radar applications in 28-nm CMOS. A two-point modulation technique is …
modulator for radar applications in 28-nm CMOS. A two-point modulation technique is …
A 12-mW 10-GHz FMCW PLL based on an integrating DAC with 28-kHz RMS-frequency-error for 23-MHz/μs slope and 1.2-GHz chirp-bandwidth
PT Renukaswamy, N Markulic… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
A 10-GHz sub-sampling phase-locked loop (PLL)(SSPLL) with wideband low-noise
frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications …
frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications …
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking …
SM Dartizio, F Buccoleri, F Tesolin… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This work presents a fast-locking and low-jitter fractional-bang-bang phase-locked loop
(BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs …
(BBPLL). To break the trade-off between jitter and locking time which is typical of BBPLLs …
A 16-GHz background-calibrated duty-cycled FMCW charge-pump PLL
PT Renukaswamy, K Vaesen… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
A 16-GHz charge-pump phase-locked loop (CP-PLL) for a robust duty-cycled frequency-
modulated continuous-wave (FMCW) radar chirp generation is presented. A duty-cycling …
modulated continuous-wave (FMCW) radar chirp generation is presented. A duty-cycling …
A Low-Spur and Low-Jitter Fractional- Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
This work presents a low-spur and low-jitter fractional-digital phase-locked loop (PLL). To
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
reduce the fractional spurs caused by the non-linearity of the digital-to-time converter (DTC) …
[HTML][HTML] 硅基毫米波雷达芯片研究现状与发展
贾海昆， 池保勇 - 电子与信息学报, 2020 - jeit.ac.cn
毫米波雷达具备全天候复杂环境下的工作能力, 在汽车雷达, 智能机器人等方面有广泛的应用.
同时, 随着半导体技术的快速发展, 硅基工艺晶体管的截止频率提升, 硅基毫米波雷达成为研究 …
同时, 随着半导体技术的快速发展, 硅基工艺晶体管的截止频率提升, 硅基毫米波雷达成为研究 …
FMCW chirp frequency error and phase noise measurement
PT Renukaswamy, N Markulic, J Craninckx - PLL Modulation and Mixed …, 2024 - Springer
In FMCW radar systems the frequency ramp nonlinearity and the synthesizer phase noise
impact the radar's ranging precision. In this chapter, a measurement method is presented …
impact the radar's ranging precision. In this chapter, a measurement method is presented …