Fast and accurate performance analysis techniques are essential in early design space
exploration and pre-silicon evaluations, including software eco-system development. In …

In-memory computing (IMC) provides a dense and parallel structure for high performance
and energy-efficient acceleration of deep neural networks (DNNs). The increased …

Weighted round-robin (WRR) arbitration provides global fairness in networks-on-chip
(NoCs) as opposed to the commonly used round-robin and priority-based arbitration …

This article proposes a Network-on-Chip (NoC) communication subsystem model on the
basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of …

With the increase in the network size, the conventional network-on-chip (NoC) imposes high
latency due to the lack of shorter paths between far nodes resulting in performance …

On-chip networks (NoCs) have become a popular choice for designing large multiprocessor
architectures. Software-based emulation is often used to perform the design verification …

Conventional mesh-based interconnection architecture is simple to implement and verify.
However, with the increase in nodes and network size, the architecture imposes high latency …

Network-on-Chip (NoC) congestion builds up during heavy traffic load and leads to wasted
link bandwidth, crippling the system performance. We propose a lightweight machine …

Fast Analysis using Finite Queuing Model for multi-layer NoCs Page 1 1 Fast Analysis using
Finite Queuing Model for multi-layer NoCs Shruti Y. Narayana1, Sumit K. Mandal2, Raid …

Homogeneous multi-core architectures have successfully exploited threadand data-level
parallelism to achieve performance and energy efficiency beyond the limits of single-core …