AI/ML algorithms and applications in VLSI design and technology

D Amuru, A Zahra, HV Vudumula, PK Cherupally… - Integration, 2023 - Elsevier
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

Energy efficient computing systems: Architectures, abstractions and modeling to techniques and standards

R Muralidhar, R Borovica-Gajic, R Buyya - ACM Computing Surveys …, 2022 - dl.acm.org
Computing systems have undergone a tremendous change in the last few decades with
several inflexion points. While Moore's law guided the semiconductor industry to cram more …

Deepem: Deep neural networks model recovery through em side-channel information leakage

H Yu, H Ma, K Yang, Y Zhao… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
Neural Network (NN) accelerators are currently widely deployed in various security-crucial
scenarios, including image recognition, natural language processing and autonomous …

PRIMAL: Power inference using machine learning

Y Zhou, H Ren, Y Zhang, B Keller, B Khailany… - Proceedings of the 56th …, 2019 - dl.acm.org
This paper introduces PRIMAL, a novel learning-based framework that enables fast and
accurate power estimation for ASIC designs. PRIMAL trains machine learning (ML) models …

Effective quadtree plus binary tree block partition decision for future video coding

Z Wang, S Wang, J Zhang, S Wang… - 2017 Data compression …, 2017 - ieeexplore.ieee.org
Block partition structure has been recognized as a crucial module in video coding scheme.
Recently, a quadtree plus binary tree (QTBT) block partition structure has been proposed in …

An energy and power consumption analysis of FPGA routing architectures

P Jamieson, W Luk, SJE Wilton… - … Conference on Field …, 2009 - ieeexplore.ieee.org
In this work, we evaluate bi-directional and unidirectional FPGA routing architectures in
terms of energy and power consumption using an updated power estimation framework …

Field programmable gate arrays for enhancing the speed and energy efficiency of quantum dynamics simulations

JM Rodrı́guez-Borbón, A Kalantar… - Journal of chemical …, 2020 - ACS Publications
We present the first application of field programmable gate arrays (FPGAs) as new,
customizable hardware architectures for carrying out fast and energy-efficient quantum …

Fast power and performance evaluation of FPGA-based wireless communication systems

J Lorandel, JC Prévotet, M Helard - IEEE Access, 2016 - ieeexplore.ieee.org
In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate
the power consumption and performance of wireless communication base-band systems …

NNReArch: a tensor program scheduling framework against neural network architecture reverse engineering

Y Luo, S Duan, C Gongye, Y Fei… - 2022 IEEE 30th Annual …, 2022 - ieeexplore.ieee.org
Architecture reverse engineering has become an emerging attack against deep neural
network (DNN) implementations. Several prior works have utilized side-channel leakage to …

Power measurement methodology for FPGA devices

R Jevtic, C Carreras - IEEE Transactions on Instrumentation …, 2010 - ieeexplore.ieee.org
The efficiency of power optimization tools depends on information on design power provided
by the power estimation models. Power models targeting different power groups can enable …