Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

M Sumalatha, PV Naganjaneyulu, KS Prasad - Microprocessors and …, 2019 - Elsevier
Abstract In recent years, Finite Impulse Response (FIR) filter plays a major role in signal
processing applications. Earlier many research papers are described the different types of …

Design of proficient two operand adder using hybrid carry select adder with FPGA implementation

V Thamizharasan, N Kasthuri - IETE Journal of Research, 2023 - Taylor & Francis
In every modern ICs the adders are essential components. Adder's performance has a
substantial impact on the architecture of signal processing, controller, the module of filter, the …

[Retracted] Design and Implementation of SOC‐Based Noncontact‐Type Level Sensing for Conductive and Nonconductive Liquids

JLM Iqbal, MS Kishore, A Ganeshan… - Advances in Materials …, 2021 - Wiley Online Library
In contrast to the existing electromechanical systems, the noncontact‐type capacitive
measurement allows for a chemically and mechanically isolated, continuous, and inherently …

A low-power vlsi implementation of rfir filter design using radix-2 algorithm with lcsla

K Satish Reddy, HN Suresh - IETE Journal of Research, 2020 - Taylor & Francis
The multimedia applications and mobile communication systems require an efficient
reconfigurable finite impulse response (RFIR) filter designs for achieving low area, power …

FPGA-Based Reconfigurable Architectures for DSP Computations

JL Mazher Iqbal, T Manikandan - Advances in Smart System Technologies …, 2021 - Springer
With extensive usage of Field Programmable Gate Arrays (FPGAs), a reconfigurable
computing platform enhances the wide variety of Digital Signal Processing (DSP) …

The vedic design-carry look ahead (VD-CLA): a smart and hardware-friendly implementation of the FIR Filter for ECG signal denoising

KB Sowmya, Chandana, MD Anjana - Advances in Multidisciplinary …, 2021 - Springer
This manuscript refers to the features of a novel finite impulse response (FIR) filter (FIRF)
architectural design to denoise electrocardiogram (ECG) signals known as Vedic design …

[PDF][PDF] A low power VLSI implementation of reconfigurable FIR filter using carry bypass adder

KS Reddy, HN Suresh - Int. J. Intell. Eng. Syst, 2018 - academia.edu
Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in Software
Defined Ratio (SDR) systems, whose filter co-efficient change dynamically during runtime. In …

[PDF][PDF] New Approach to Memory Less Design and Look-Up-Table Realization for Low-Complexity Reconfigurable Digital FIR Filter Architectures

JLM Iqbal, S Varadarajan - WSEAS Transactions on Systems, 2013 - wseas.us
Low-complexity and high-speed digital finite impulse response (FIR) filter is widely used in
various signal processing and image processing applications because of less area, low …

Low power and low area multiplier and accumulator block for efficient implementation of FIR filter

JLM Iqbal, G Narayan, T Manikandan… - Low Power Designs in … - taylorfrancis.com
In communication system applications, the need for efficient design and implementation of
the finite impulse response (FIR) filter is essential. Realization of such a filter with high bit …

Low-power VLSI design using clock-gated technique

JLM Iqbal, ASM Priyadharson, T Manikandan… - Low Power Designs in … - taylorfrancis.com
With the advancement in VLSI (very large-scale integration) innovation and modest devices,
power dissipation has developed as a critical factor while considering execution and territory …